An 8Gb/s adaptive DFE with level calibration using training data pattern for mobile DRAM interface

Abstract

An 8Gb/s adaptive decision feedback equalizer (DFE) using training sequence is designed in a 65nm CMOS. The training data pattern ‘10111111’ is used to detect distorted data level periodically. The tap coefficients are automatically adjusted during the training mode by compensating for the difference between the distorted data level and ideal high DC level. The power consumption is 10.4mW at 1.05V supply voltage and the adaptation time is 90ns. The simulation results show the improvement of data eye after training the tap coefficients. The data eye width and height are improved from 0.36UI to 0.84UI and from 40mV to 90mV, respectively.