Tailor-made synaptic dynamics based on memristive devices

Abstract

The proliferation of machine learning algorithms in everyday applications such as image recognition or language translation has increased the pressure to adapt underlying computing architectures towards these algorithms. Application specific integrated circuits (ASICs) such as the Tensor Processing Units by Google, Hanguang by Alibaba or Inferentia by Amazon Web Services were designed specifically for machine learning algorithms and have been able to outperform CPU based solutions by great margins during training and inference. As newer generations of chips allow handling of and computation on more and more data, the size of neural networks has dramatically increased, while the challenges they are trying to solve have become more complex. Neuromorphic computing tries to take inspiration from biological information processing systems, aiming to further improve the efficiency with which these networks can be trained or the inference can be performed. Enhancing neuromorphic computing architectures with memristive devices as non-volatile storage elements could potentially allow for even higher energy efficiencies. Their ability to mimic synaptic plasticity dynamics brings neuromorphic architectures closer to the biological role models. So far, memristive devices are mainly investigated for the emulation of the weights of neural networks during training and inference as their non-volatility would enable both processes in the same location without data transfer. In this paper, we explore realisations of different synapses build from memristive ReRAM devices, based on the Valence Change Mechanism. These synapses are the 1R synapse, the NR synapse and the 1T1R synapse. For the 1R synapse, we propose three dynamical regimes and explore their performance through different synapse criteria. For the NR synapse, we discuss how the same dynamical regimes can be addressed in a more reliable way. We also show experimental results measured on ZrOx devices to support our simulation based claims. For the 1T1R synapse, we explore the trade offs between the connection direction of the ReRAM device and the transistor. For all three synapse concepts we discuss the impact of device-to-device and cycle-to-cycle variability. Additionally, the impact of the stimulation mode on the observed behavior is discussed.