{"title":"Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random VT Variations on Timing","authors":"B. K. Boroujeni, C. Piguet, Y. Leblebici","doi":"10.1007/978-3-642-17752-1_17","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Workshop on Power and Timing Modeling, Optimization and Simulation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1007/978-3-642-17752-1_17","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
