Revisited Design of Short-pulse Power Gated Approach of Subthreshold Leakage Reduction Technique in Combinational Circuits

Abstract

Low power consumption is the ultimate goal of the circuit designers of any application and specifically, the life time of event-driven nature of low duty cycle applications like Wireless Sensor Networks (WSN) relies on the design of power-stringent battery-operated devices. At all the hierarchical level of the sensor nodes, low duty cycling is the practicing solution in saving the unwanted power consumption. However, the rapid power squanderer at the sleep state of the circuit is the subthreshold leakage. The exact saving of the leakage can be done by suppressing the short-channel effects of the transistors only at the circuit-level and the two techniques Modified Power Gating (MPG) and Short-pulse POwer Gated Approach (SPOGA, hereafter called as SPOGA_old) are proposed and implemented in the combinational circuits in the previous works of the research. In spite of good subthreshold leakage reduction, the limitations of the proposed techniques are loading effect, state-retention and leakage estimation method. In order to provide an efficient sleep state subthreshold leakage reduction in combinational circuits of low duty cycle application, the limitations are addressed with a revisited design of SPOGA_old, called as SPOGA technique. The illustration of the proposed SPOGA technique with CMOS inverter is done using Cadence GPDK090. From the simulation results, it is clearly seen that the Subthreshold Leakage Reduction Ratio (SLRR) is high and proved the efficacy of the SPOGA technique in subthreshold leakage reduction.