Automation of Communication Refinement and Hardware Synthesis within a System-Level Design Methodology

Abstract

Traditional register-transfer level design methodologies for systems-on-chip are failing to keep up with the growing complexity of embedded applications and architectures. A well-known solution is to raise the level of design abstraction by using system-level methodologies. The refinement from system-level specifications to concrete implementations is an essential step in a system-level design methodology. This article presents a novel methodology for the refinement from transaction-level communications to pin- and cycle-accurate protocols as well as the generation of synthesizable hardware from system-level specifications. Automatic communication refinement and hardware synthesis were successfully applied to a rover guiding system. Hand-coded and automatically generated register-transfer level modules of the rover are compared. Results show that a hardware/software implementation of the guiding system using generated register-transfer level modules has overheads of less than one percent in latency and hardware area when compared to an implementation using hand-coded modules.