Two statistical coding tools - the context-based adaptive variable length coding (CAVLC) and the context-based adaptive binary arithmetic coding (CABAC) - have been adopted in different profiles of the H.264/AVC video coding standard. The throughput at the statistical coding stage is mainly constrained by the high data dependency and sequential coding nature of CAVLC and CABAC Many hardware designs have been proposed to remove the bottlenecks and accelerate statistical coding and decoding of H.264/AVC In this paper, different implementation strategies of CAVLC and CABAC encoder and decoder architectures are investigated. The strategies are evaluated using criteria such as circuit area, processing time, and power consumption. The three most important techniques used are: multi-symbol processing, table lookup optimization, and critical path reduction by data prefetch I pre-calculation. In the discussion of CABAC encoder our implementation strategies are introduced and compared with other reported designs.
{"title":"Implementation Strategies for Statistical Codec Designs in H.264/AVC Standard","authors":"X. Tian, T. M. Le, Xi Jiang, Y. Lian","doi":"10.1109/RSP.2008.22","DOIUrl":"https://doi.org/10.1109/RSP.2008.22","url":null,"abstract":"Two statistical coding tools - the context-based adaptive variable length coding (CAVLC) and the context-based adaptive binary arithmetic coding (CABAC) - have been adopted in different profiles of the H.264/AVC video coding standard. The throughput at the statistical coding stage is mainly constrained by the high data dependency and sequential coding nature of CAVLC and CABAC Many hardware designs have been proposed to remove the bottlenecks and accelerate statistical coding and decoding of H.264/AVC In this paper, different implementation strategies of CAVLC and CABAC encoder and decoder architectures are investigated. The strategies are evaluated using criteria such as circuit area, processing time, and power consumption. The three most important techniques used are: multi-symbol processing, table lookup optimization, and critical path reduction by data prefetch I pre-calculation. In the discussion of CABAC encoder our implementation strategies are introduced and compared with other reported designs.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128458323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
ASIP-based implementations constitute a key trend in SoC design enabling optimal tradeoffs between performance and flexibility. This paper details a case study of an ASIP-based implementation of a high throughput flexible turbo decoder. It introduces turbo decoding application and proposes an Application-Specific Instruction-set Processor with SIMD architecture, a specialized and extensible instruction-set, and 6-stages pipeline control. The proposed ASIP is developed in LISA language and generated automatically using the Processor Designer framework from CoWare. The paper illustrates how the automatic generated RTL code of the ASIP can be adapted for a rapid prototyping on PPGA reconfigurable logic and memory resources. Tor a Xilinx Virtex-II Pro PPGA, a single ASIP prototype occupies 68% of PPGA resources and achieves a 6.3 Mbit/s throughput when decoding a double binary turbo code with 5 iterations.
基于api的实现构成了SoC设计的关键趋势，实现了性能和灵活性之间的最佳权衡。本文详细介绍了一个基于api实现的高吞吐量灵活涡轮解码器的案例研究。介绍了turbo译码的应用，提出了一种基于SIMD架构的专用指令集处理器、专用可扩展指令集和6级流水线控制。所提出的ASIP是用LISA语言开发的，并使用CoWare中的Processor Designer框架自动生成。本文阐述了ASIP的自动生成RTL代码如何适应PPGA可重构逻辑和内存资源的快速原型设计。对于Xilinx Virtex-II Pro PPGA，单个ASIP原型占用PPGA资源的68%，在解码双二进制turbo码的5次迭代时实现6.3 Mbit/s的吞吐量。
{"title":"From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding","authors":"O. Muller, A. Baghdadi, M. Jézéquel","doi":"10.1109/RSP.2008.16","DOIUrl":"https://doi.org/10.1109/RSP.2008.16","url":null,"abstract":"ASIP-based implementations constitute a key trend in SoC design enabling optimal tradeoffs between performance and flexibility. This paper details a case study of an ASIP-based implementation of a high throughput flexible turbo decoder. It introduces turbo decoding application and proposes an Application-Specific Instruction-set Processor with SIMD architecture, a specialized and extensible instruction-set, and 6-stages pipeline control. The proposed ASIP is developed in LISA language and generated automatically using the Processor Designer framework from CoWare. The paper illustrates how the automatic generated RTL code of the ASIP can be adapted for a rapid prototyping on PPGA reconfigurable logic and memory resources. Tor a Xilinx Virtex-II Pro PPGA, a single ASIP prototype occupies 68% of PPGA resources and achieves a 6.3 Mbit/s throughput when decoding a double binary turbo code with 5 iterations.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123179832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Plishker, N. Sane, Mary Kiemb, K. Anand, S. Bhattacharyya
Dataflow formalisms have provided designers of digital signal processing systems with optimizations and guarantees to arrive at quality prototypes quickly. As system complexity increases, designers are expressing more types of behavior in dataflow languages to retain these implementation benefits. While the semantic range of DSP-oriented dataflow models has expanded to cover quasi-static and dynamic applications, efficient functional simulation of such applications has not. Complexity in scheduling and modeling has impeded efforts towards functional simulation that matches the final implementation. We provide this functionality by introducing a new dataflow model of computation, called enable-invoke dataflow (EIDF), that supports flexible and efficient prototyping of dataflow-based application representations. EIDF permits the natural description of actors for dynamic and static dataflow models. We integrate EIDF into the dataflow interchange format (DIF) package and demonstrate the approach on the design of a polynomial evaluation accelerator targeting an FPGA implementation. Our experiments show that a design environment based on EIDF can achieve functionally-correct simulation compared to Verilog, allowing the application designer to arrive at a verified functional simulation faster, and therefore at a functional prototype much more quickly than traditional design practices.
{"title":"Functional DIF for Rapid Prototyping","authors":"W. Plishker, N. Sane, Mary Kiemb, K. Anand, S. Bhattacharyya","doi":"10.1109/RSP.2008.32","DOIUrl":"https://doi.org/10.1109/RSP.2008.32","url":null,"abstract":"Dataflow formalisms have provided designers of digital signal processing systems with optimizations and guarantees to arrive at quality prototypes quickly. As system complexity increases, designers are expressing more types of behavior in dataflow languages to retain these implementation benefits. While the semantic range of DSP-oriented dataflow models has expanded to cover quasi-static and dynamic applications, efficient functional simulation of such applications has not. Complexity in scheduling and modeling has impeded efforts towards functional simulation that matches the final implementation. We provide this functionality by introducing a new dataflow model of computation, called enable-invoke dataflow (EIDF), that supports flexible and efficient prototyping of dataflow-based application representations. EIDF permits the natural description of actors for dynamic and static dataflow models. We integrate EIDF into the dataflow interchange format (DIF) package and demonstrate the approach on the design of a polynomial evaluation accelerator targeting an FPGA implementation. Our experiments show that a design environment based on EIDF can achieve functionally-correct simulation compared to Verilog, allowing the application designer to arrive at a verified functional simulation faster, and therefore at a functional prototype much more quickly than traditional design practices.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121831748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
When teaching robotics, we have a number of constraints and desires to satisfy. We are limited by the time available to teach a class, so we need a robotic system that our students can get up to speed on quickly and easily. We are limited by robot availability, in the robots that are on hand, but also because manufacturers of inexpensive teaching robots tend to go bankrupt or change focus quickly, making it difficult to purchase new robots with the same interface as previous models. Thus, we desire an interface easily adaptable to new robots. Finally, we have recently become interested in teaching techniques for dealing with teams of possibly heterogeneous robots. All existing systems that we examined fall short in one or more of these areas, prompting our development of the The multi-agent Java interface controller (MAJIC). MAJIC was designed from the bottom up with modern software engineering principles. The interface is easy to use and learn, can be quickly adapted to new robots, and allows control of multiple robots simultaneously. This paper presents the design of this system, highlighting rapid development and clarity compared with other systems.
{"title":"MAJIC: A Java Application for Controlling Multiple, Heterogeneous Robotic Agents","authors":"Gregory P. Ball, K. Squire, C. Martell, M. Shing","doi":"10.1109/RSP.2008.30","DOIUrl":"https://doi.org/10.1109/RSP.2008.30","url":null,"abstract":"When teaching robotics, we have a number of constraints and desires to satisfy. We are limited by the time available to teach a class, so we need a robotic system that our students can get up to speed on quickly and easily. We are limited by robot availability, in the robots that are on hand, but also because manufacturers of inexpensive teaching robots tend to go bankrupt or change focus quickly, making it difficult to purchase new robots with the same interface as previous models. Thus, we desire an interface easily adaptable to new robots. Finally, we have recently become interested in teaching techniques for dealing with teams of possibly heterogeneous robots. All existing systems that we examined fall short in one or more of these areas, prompting our development of the The multi-agent Java interface controller (MAJIC). MAJIC was designed from the bottom up with modern software engineering principles. The interface is easy to use and learn, can be quickly adapted to new robots, and allows control of multiple robots simultaneously. This paper presents the design of this system, highlighting rapid development and clarity compared with other systems.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131523882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
RealSpec is a declarative executable language for the prototyping of concurrent and real-time systems based on a dataflow functional model. RealSpec is developed on top of Lucid dataflow programming language by enhancing Lucid with features for real-time systems. This paper provides basic RealSpec language constructs for modeling concurrent processes, multithreading, and resource modeling. The producer consumer example is used to demonstrate the applicability of these language features.
{"title":"RealSpec: An Executable Specification Language for Prototyping Concurrent Systems","authors":"A. Khwaja, J. E. Urban","doi":"10.1109/RSP.2008.9","DOIUrl":"https://doi.org/10.1109/RSP.2008.9","url":null,"abstract":"RealSpec is a declarative executable language for the prototyping of concurrent and real-time systems based on a dataflow functional model. RealSpec is developed on top of Lucid dataflow programming language by enhancing Lucid with features for real-time systems. This paper provides basic RealSpec language constructs for modeling concurrent processes, multithreading, and resource modeling. The producer consumer example is used to demonstrate the applicability of these language features.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115033260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the challenges encountered during the process of moving an MPEG4 decoder implementation from Rise based platforms to CELL processor. It presents multiple implementations of MPEG4 video decoder on a CELL processor, using different software partitioning and mapping schemes. The approach starts from a generic representation of an MPEG4 video decoder, from which multiple customized MPEG4 video decoders can be obtained (i.e. different number of tasks, video resolutions, frame-rates, etc). Each of these configurations of MPEG4 video decoders was mapped and executed on a CELL processor. During previous works, this was already realized using multi-RISC based multi processor system on chip (MPSoc) platforms. However, by changing to CELL processors, new challenges and problems appeared. They must be considered and solved, in order to obtain a running MPEG4 video decoder on CELL. This paper presents these challenges and problems, along with some solutions. Finally, some performance results are presented for different MPEG4 video decoders implementations on a CELL processor. This paper is focusing on the portation only, and does not cover the final optimization phase using CELL processor specific code optimization techniques.
{"title":"Software for Multi Processor System on Chip: Moving an MPEG4 Decoder from Generic RISC Platforms to CELL","authors":"Ludovic Demontes, M. Bonaciu, P. Amblard","doi":"10.1109/RSP.2008.21","DOIUrl":"https://doi.org/10.1109/RSP.2008.21","url":null,"abstract":"This paper presents the challenges encountered during the process of moving an MPEG4 decoder implementation from Rise based platforms to CELL processor. It presents multiple implementations of MPEG4 video decoder on a CELL processor, using different software partitioning and mapping schemes. The approach starts from a generic representation of an MPEG4 video decoder, from which multiple customized MPEG4 video decoders can be obtained (i.e. different number of tasks, video resolutions, frame-rates, etc). Each of these configurations of MPEG4 video decoders was mapped and executed on a CELL processor. During previous works, this was already realized using multi-RISC based multi processor system on chip (MPSoc) platforms. However, by changing to CELL processors, new challenges and problems appeared. They must be considered and solved, in order to obtain a running MPEG4 video decoder on CELL. This paper presents these challenges and problems, along with some solutions. Finally, some performance results are presented for different MPEG4 video decoders implementations on a CELL processor. This paper is focusing on the portation only, and does not cover the final optimization phase using CELL processor specific code optimization techniques.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"339 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122850197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. I. Moreno, K. Popovici, Ney Laert Vilar Calazans, A. Jerraya
Current embedded applications are migrating from single processor-based systems to intensive data communication requiring multiprocessing. The performance demanded by these applications requires the use of heterogeneous multiprocessing architectures in a single chip (MPSoCs) endowed with complex communication infrastructures, such as networks on chip or NoCs. NoC parameter choices, such as network dimensioning, topology, routing algorithm, and buffer sizing then become essential aspects for optimizing the implementation of such complex systems. This paper presents NoC models that allow evaluating communication architectures through the variation of parameters during MPSoC design. Applicability of the concepts is demonstrated through two heterogeneous MPSoC case studies: an MJPEG decoder and an H.264 encoder.
{"title":"Integrating Abstract NoC Models within MPSoC Design","authors":"E. I. Moreno, K. Popovici, Ney Laert Vilar Calazans, A. Jerraya","doi":"10.1109/RSP.2008.29","DOIUrl":"https://doi.org/10.1109/RSP.2008.29","url":null,"abstract":"Current embedded applications are migrating from single processor-based systems to intensive data communication requiring multiprocessing. The performance demanded by these applications requires the use of heterogeneous multiprocessing architectures in a single chip (MPSoCs) endowed with complex communication infrastructures, such as networks on chip or NoCs. NoC parameter choices, such as network dimensioning, topology, routing algorithm, and buffer sizing then become essential aspects for optimizing the implementation of such complex systems. This paper presents NoC models that allow evaluating communication architectures through the variation of parameters during MPSoC design. Applicability of the concepts is demonstrated through two heterogeneous MPSoC case studies: an MJPEG decoder and an H.264 encoder.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"16 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116912032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Christopher Spies, P. Zipf, M. Glesner, H. Klingbeil
This paper describes a high-level simulation model and its application to determine bandwidth requirements for the hardware implementation of a digital control system. The simulation model is based on Ptolemy II and describes a heavy-ion synchrotron and its control systems for resonance frequency, beam phase, and cavity synchronisation. Simulations are used to verify the suitability of the chosen system structure and to obtain minimum update rates for the coefficients of the adaptive digital controllers. These update rates translate into bandwidth requirements for a fiber optical network connecting the different controller subsystems. Our modelling approach as well as our method to determine the low-level requirements are described in detail and simulation results are presented and discussed.
{"title":"Bandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy II","authors":"Christopher Spies, P. Zipf, M. Glesner, H. Klingbeil","doi":"10.1109/RSP.2008.26","DOIUrl":"https://doi.org/10.1109/RSP.2008.26","url":null,"abstract":"This paper describes a high-level simulation model and its application to determine bandwidth requirements for the hardware implementation of a digital control system. The simulation model is based on Ptolemy II and describes a heavy-ion synchrotron and its control systems for resonance frequency, beam phase, and cavity synchronisation. Simulations are used to verify the suitability of the chosen system structure and to obtain minimum update rates for the coefficients of the adaptive digital controllers. These update rates translate into bandwidth requirements for a fiber optical network connecting the different controller subsystems. Our modelling approach as well as our method to determine the low-level requirements are described in detail and simulation results are presented and discussed.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126105528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Increased dynamics of the embedded devices market makes reduced time-to-market emerge as one of most challenging tasks in modern embedded system design. The complexity of Multiprocessor Systems-on-Chip (MPSoCs) rapidly increases and Networks-on-Chips (NoCs) have emerged as design strategy to cope with it. In order to allow fast generation of these platforms in the development phase, a full design flow is required. On the other hand, modern FPGAs provide the possibility for fast and low-cost prototyping, representing an efficient response to these needs. In this paper we present a framework, based on the Xilinx Embedded Development Kit (EDK) design flow, for the generation of MPSoCs based on NoCs. The tool provides system designers with the possibility to easily and quickly generate desired architectures that can be helpful for testing, debugging and verifying purposes. Our integrated design flow takes as input a textual description of the system and produces as final result a configuration bitstream file. The framework has been tested and verified on a Xilinx Virtex-II Pro board.
{"title":"An Automated Design Flow for NoC-based MPSoCs on FPGA","authors":"S. Lukovic, Leandro Fiorin","doi":"10.1109/RSP.2008.31","DOIUrl":"https://doi.org/10.1109/RSP.2008.31","url":null,"abstract":"Increased dynamics of the embedded devices market makes reduced time-to-market emerge as one of most challenging tasks in modern embedded system design. The complexity of Multiprocessor Systems-on-Chip (MPSoCs) rapidly increases and Networks-on-Chips (NoCs) have emerged as design strategy to cope with it. In order to allow fast generation of these platforms in the development phase, a full design flow is required. On the other hand, modern FPGAs provide the possibility for fast and low-cost prototyping, representing an efficient response to these needs. In this paper we present a framework, based on the Xilinx Embedded Development Kit (EDK) design flow, for the generation of MPSoCs based on NoCs. The tool provides system designers with the possibility to easily and quickly generate desired architectures that can be helpful for testing, debugging and verifying purposes. Our integrated design flow takes as input a textual description of the system and produces as final result a configuration bitstream file. The framework has been tested and verified on a Xilinx Virtex-II Pro board.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126409694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mateusz Majer, S. Wildermann, Josef Angermeier, S. Hanke, J. Teich
Current graphic cards include advanced graphic processing units to accelerate the rendering of 3D objects with millions of polygons. As object models grow in complexity, the rendering approach based on points as primitives is regarded superior in terms of scalability and efficiency. Next generation graphic cards could contain reconfigurable fabrics, similar to those implemented in current FPGAs, to offer two advantages: a) fast rendering units and b) new mechanisms for custom, run-time exchangeable accelerators. In this paper, we propose a hardware point-rendering architecture tailored specifically for reconfigurable systems. The presented implementation on a real FPGA-based platform demonstrates on the one hand the effectiveness of the approach and on the other hand it provides valuable insights into possible future improvements for this problem scenario.
{"title":"Co-design Architecture and Implementation for Point-Based Rendering on FPGAs","authors":"Mateusz Majer, S. Wildermann, Josef Angermeier, S. Hanke, J. Teich","doi":"10.1109/RSP.2008.23","DOIUrl":"https://doi.org/10.1109/RSP.2008.23","url":null,"abstract":"Current graphic cards include advanced graphic processing units to accelerate the rendering of 3D objects with millions of polygons. As object models grow in complexity, the rendering approach based on points as primitives is regarded superior in terms of scalability and efficiency. Next generation graphic cards could contain reconfigurable fabrics, similar to those implemented in current FPGAs, to offer two advantages: a) fast rendering units and b) new mechanisms for custom, run-time exchangeable accelerators. In this paper, we propose a hardware point-rendering architecture tailored specifically for reconfigurable systems. The presented implementation on a real FPGA-based platform demonstrates on the one hand the effectiveness of the approach and on the other hand it provides valuable insights into possible future improvements for this problem scenario.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125109324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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