MEDIATOR - A Mixed Criticality Deadline Honored Arbiter for Multi-core Real-time Systems

A. S. Nair, L. Colaco, Geeta Patil, B. Raveendran, S. Punnekkat
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引用次数: 4

Abstract

Multi-core systems are the potential enablers of the overwhelming growth of mixed criticality systems. There exist challenges to the widespread usage of multi-core in mixed criticality systems due to the non-predictive resource access timings. In this work, we present a Last Level Cache (LLC) access control mechanism, MEDIATOR that guarantees high criticality job executions without deadline misses for multi-core mixed-criticality systems. In MEDIATOR, the LLC access requests of lower criticality jobs are honored, if and only if there exists adequate slack for higher criticality jobs. The legacy First-In, First-Out (FIFO) arbiter has high deadline miss probability for high criticality jobs. The MEDIATOR behaves differently from legacy arbiter only when slack of higher criticality jobs is less. It guarantees successful execution of higher criticality jobs by blocking low criticality jobs. The experimental evaluation with software simulation and hardware implementation confirms the successful completion of high criticality jobs with LLC contention by honoring low criticality jobs whenever possible. Simulation results with the help of synthetic benchmark suites show successful completion of high criticality jobs at a high workload where legacy arbiter fails. The hardware design synthesized in Cadence using Genus Synthesis Solution 17.21 shows that MEDIATOR takes negligibly small time and energy overhead to achieve the same.
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一个多核实时系统的混合临界截止日期仲裁器
多核系统是混合临界系统压倒性增长的潜在推动者。由于资源访问时序的不可预测性,使得多核在混合临界系统中的广泛应用面临挑战。在这项工作中,我们提出了一种最后一级缓存(LLC)访问控制机制,MEDIATOR,它保证多核混合临界系统的高临界作业执行不会错过截止日期。在MEDIATOR中,当且仅当存在足够的空闲来处理较高临界作业时,较低临界作业的LLC访问请求才会被执行。传统的先进先出(FIFO)仲裁器对于高关键作业具有很高的截止日期错过概率。只有当较高临界作业的空闲较少时,MEDIATOR的行为才与遗留仲裁器不同。它通过阻塞低临界任务来保证高临界任务的成功执行。通过软件仿真和硬件实现的实验评估,证实了通过尽可能地尊重低临界任务,成功完成具有LLC争用的高临界任务。在合成基准套件的帮助下,仿真结果显示在遗留仲裁器失效的高工作负载下,成功完成了高关键作业。使用Genus Synthesis Solution 17.21在Cadence中合成的硬件设计表明,MEDIATOR只需很小的时间和能量开销即可实现相同的目标。
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