Off current adjustment in ultra-thin SOI MOSFETs

Abstract

This work reports a detailed study of nanoscale ultra-thin (UT) SOI MOSFETs for low power applications. Partially depleted (PD) and fully depleted (FD) NMOS and PMOS devices with a wide range of gate lengths down to 25 nm and silicon thicknesses of 25 nm and 16 nm have been analysed. Gate oxide thicknesses of 2.5 nm and 1.8 nm have also been compared. We demonstrate off current adjustment by channel implantation whereby, together with work function engineering, a suitable solution for multiple Vt SOI CMOS technology could be provided.