Intrinsic Parameter Fluctuation and Process Variation Effect of Vertically Stacked Silicon Nanosheet Complementary Field-Effect Transistors

Abstract

We study the variability of vertically stacked gate-all-around silicon nanosheet (GAA Si NS) complementary field-effect transistors (CFETs). The process variation effect (PVE), the work function fluctuation (WKF), and the random dopant fluctuation (RDF) of CFETs are statistically estimated using an experimentally validated device simulation technique. Among five factors of PVE, the channel thickness (TNch/TPch), the channel width (Wch), and the gate length (LG) are significant. Owing to superior GAA channel control and increased effective gate area, both WKF and RDF are suppressed. Notably, the PVE on both N-/P-FETs of GAA Si CFET induce the largest off-state current fluctuations of 80% and 278%, respectively, because the device characteristic is very sensitive to the layer thickness and width of channel.