Exploiting bit-level parallelism in Boolean matrix operations for graph analysis

D. J. Jackson, D.M. Whiteside, L. Wurtz
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Abstract

A number of important characteristics for a graph, which may represent a set of parallel application tasks or a parallel computer architecture, can be extracted by analyzing the Boolean matrix corresponding to the graph. The characteristic of concern is the determination of minimum path lengths for various classes of regularly structured graphs. All the example graphs vary in terms of connectivity and sparsity and provide a suitable testbed for the analysis of the various algorithms used in determining powers of the Boolean matrices. Improvements for these algorithms are introduced which exploit the Boolean nature of the matrices and the inherent bit-level parallelism available in any N-bit computer system. An algorithm is introduced which exploits this bit-level parallelism and a number of graphs were analyzed utilizing a high-performance IBM RS/6000 workstation to demonstrate the merits of the algorithm.<>
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利用图分析布尔矩阵操作中的位级并行性
通过分析图对应的布尔矩阵,可以提取图的一些重要特征,这些特征可以表示一组并行应用程序任务或并行计算机体系结构。问题的特点是确定各种规则结构图的最小路径长度。所有示例图在连通性和稀疏性方面都有所不同,并为分析用于确定布尔矩阵幂的各种算法提供了合适的测试平台。介绍了这些算法的改进,这些改进利用了矩阵的布尔性质和任何n位计算机系统中可用的固有的位级并行性。介绍了一种利用这种位级并行性的算法,并利用高性能IBM RS/6000工作站分析了一些图形,以证明该算法的优点。
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