A 0.4V 2.02fJ/conversion-step 10-bit hybrid SAR ADC with time-domain quantizer in 90nm CMOS

Yan-Jiun Chen, C. Hsieh
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引用次数: 26

Abstract

This paper presents an ultra-low voltage and power efficient 10-bit hybrid successive-approximation register (SAR) analog-to-digital converter (ADC). To reduce the total amount of capacitance and relieve requirement of comparator, we propose a hybrid architecture composed of coarse and fine conversions by 7-bit SAR ADC and 3.5-bit time-domain quantizer, respectively. Using residue voltages generated by coarse ADC and converting it to time-domain, the fine ADC detects the least three bits with 0.5-bit redundancy by Vernier delay structure. At 250KS/s and Nyquist rate input, the ADC prototype fabricated in 90nm CMOS consumes 200nW at 0.4V supply. It achieves a SNDR of 53.7db and a resulting FoM of 2.02-fJ/conv.-step.
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一种带时域量化器的0.4V 2.02fJ/转换步长10位混合SAR ADC
提出了一种超低电压、低功耗的10位混合连续逼近寄存器(SAR)模数转换器(ADC)。为了减少电容总量,减轻对比较器的要求,我们提出了一种由7位SAR ADC和3.5位时域量化器分别组成的粗转换和精转换混合架构。精细ADC利用粗ADC产生的剩余电压,将其转换为时域,通过游标延迟结构检测出至少3位,冗余为0.5位。在250KS/s和奈奎斯特速率输入下,用90nm CMOS制作的ADC原型在0.4V电源下消耗200nW。SNDR为53.7db, FoM为2.02 fj /con . step。
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