{"title":"Interconnect modeling with the existence of line inductance","authors":"M. El-Moursy, H. Shawkey","doi":"10.1142/S021812661250082X","DOIUrl":null,"url":null,"abstract":"Simple uniform reduced order model is used to model an RLC interconnect line. Waveform characterization is used to evaluate the accuracy of the adopted models. As compared to RC lines, less than five times the number of sections is sufficient to model RLC lines. Look-up tables are provided to simplify the process of choosing the best interconnect section model to characterize an RLC interconnect line. The tables are shown to be accurate for wide range of relative impedance of the driver, the line, and the load. The tables provide a simple and quick mean to characterize an RLC interconnect which is necessary for performance evaluation in digital circuits. The presented model reduces the simulation time while keeping the simulation accuracy. The simulation time can be reduced by up to 72% with less than 10% reduction in accuracy using the provided tables.","PeriodicalId":125634,"journal":{"name":"2011 Saudi International Electronics, Communications and Photonics Conference (SIECPC)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Saudi International Electronics, Communications and Photonics Conference (SIECPC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1142/S021812661250082X","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Simple uniform reduced order model is used to model an RLC interconnect line. Waveform characterization is used to evaluate the accuracy of the adopted models. As compared to RC lines, less than five times the number of sections is sufficient to model RLC lines. Look-up tables are provided to simplify the process of choosing the best interconnect section model to characterize an RLC interconnect line. The tables are shown to be accurate for wide range of relative impedance of the driver, the line, and the load. The tables provide a simple and quick mean to characterize an RLC interconnect which is necessary for performance evaluation in digital circuits. The presented model reduces the simulation time while keeping the simulation accuracy. The simulation time can be reduced by up to 72% with less than 10% reduction in accuracy using the provided tables.