{"title":"Analysing real-time communications: controller area network (CAN)","authors":"K. Tindell, H. Hanssmon, A. Wellings","doi":"10.1109/REAL.1994.342710","DOIUrl":null,"url":null,"abstract":"The increasing use of communication networks in time-critical applications presents engineers with fundamental problems with the determination of response times of communicating distributed processes. Although there has been some work on the analysis of communication protocols, most of this is for idealised networks. Experience with single-processor scheduling analysis has shown that models which abstract away from implementation details are at best very pessimistic, and at worst lead to an unschedulable system being deemed schedulable. In this paper, we derive an idealised scheduling analysis for the CAN real-time bus, and then study two actual interface chips to see how the analysis can be applied.<<ETX>>","PeriodicalId":374952,"journal":{"name":"1994 Proceedings Real-Time Systems Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"467","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1994 Proceedings Real-Time Systems Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/REAL.1994.342710","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 467
Abstract
The increasing use of communication networks in time-critical applications presents engineers with fundamental problems with the determination of response times of communicating distributed processes. Although there has been some work on the analysis of communication protocols, most of this is for idealised networks. Experience with single-processor scheduling analysis has shown that models which abstract away from implementation details are at best very pessimistic, and at worst lead to an unschedulable system being deemed schedulable. In this paper, we derive an idealised scheduling analysis for the CAN real-time bus, and then study two actual interface chips to see how the analysis can be applied.<>
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