{"title":"Current reference scheme for multilevel phase-change memory sensing","authors":"A. Cabrini, F. Gallazzi, G. Torelli","doi":"10.1109/ESSCIRC.2011.6044996","DOIUrl":null,"url":null,"abstract":"This paper presents a current reference for read and verify operations in multilevel phase-change memories (PCMs). The circuit is able to track the temperature behaviour of the PCM cell current over a temperature range from −40 °C to 80 °C, as is necessary to meet the stringent requirements of multilevel PCM sensing. The proposed scheme is based on an MOS transistor biased in saturation below its zero temperature coefficient (ZTC) point. Only room temperature trimming at wafer sort is required to adjust the value and the temperature dependence of the generated current. Experimental results showed good agreement with experimental data on PCM cells. The error in the programmed temperature coefficient is kept within 10% in any process condition.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Proceedings of the ESSCIRC (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2011.6044996","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
This paper presents a current reference for read and verify operations in multilevel phase-change memories (PCMs). The circuit is able to track the temperature behaviour of the PCM cell current over a temperature range from −40 °C to 80 °C, as is necessary to meet the stringent requirements of multilevel PCM sensing. The proposed scheme is based on an MOS transistor biased in saturation below its zero temperature coefficient (ZTC) point. Only room temperature trimming at wafer sort is required to adjust the value and the temperature dependence of the generated current. Experimental results showed good agreement with experimental data on PCM cells. The error in the programmed temperature coefficient is kept within 10% in any process condition.
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