Impact of through silicon vias on front-end-of-line performance after thermal cycling and thermal storage

Abstract

The effect of thermal cycling, accelerated thermal storage and long-term storage at room temperature on the performance of FEOL devices integrated together with through silicon vias (TSVs) is studied. The transistor performance is used as monitor of stress induced in the Si by the TSV. It is observed that storage at high temperatures increases the stress in the Si induced by the TSV while thermal cycling and long- term storage at room temperature decreases this stress. These stress variations are hypothesized to be due to creep of copper in the TSV.