A NUCA model for embedded systems cache design

Abstract

Embedded applications require high performance processors integrating fast and low-power cache. Dynamic non-uniform cache architectures (D-NUCA) have been proposed to overcome the performance limit introduced by wire delays when designing large cache. In this paper, we propose alternative designs of D-NUCA cache, namely triangular D-NUCA cache, to reduce power consumption and silicon area occupancy of D-NUCA cache. We compare the performances of triangular D-NUCA cache with conventional rectangular organization. Results show that our approach is particular useful in the embedded applications domain, as it permits the utilization of half-sized NUCA cache with performance improvements.