Pub Date : 2005-09-22DOI: 10.1109/ESTMED.2005.1518092
Soner Yaldiz, A. Demir, S. Tasiran, P. Ienne, Y. Leblebici
We present a hybrid energy management technique that exploits the variability of and correlations among the computational loads of tasks in a real-time application with soft timing constraints. In our technique, task load variability and correlations are captured in stochastic models that incorporate certain salient features and essential characteristics of the application. We use the stochastic models in formulating and solving the energy management problem for applications with soft timing constraints running on multiprocessor systems with dynamic voltage scaling (DVS). We present a novel optimization formulation for minimizing average energy consumption while providing a probabilistic guarantee for satisfying timing constraints. We compare our stochastic models and energy management scheme with other models and schemes that do not capture/exploit either the variability of or the correlations among the computational loads of tasks.
{"title":"Characterizing and exploiting task load variability and correlation for energy management in multi core systems","authors":"Soner Yaldiz, A. Demir, S. Tasiran, P. Ienne, Y. Leblebici","doi":"10.1109/ESTMED.2005.1518092","DOIUrl":"https://doi.org/10.1109/ESTMED.2005.1518092","url":null,"abstract":"We present a hybrid energy management technique that exploits the variability of and correlations among the computational loads of tasks in a real-time application with soft timing constraints. In our technique, task load variability and correlations are captured in stochastic models that incorporate certain salient features and essential characteristics of the application. We use the stochastic models in formulating and solving the energy management problem for applications with soft timing constraints running on multiprocessor systems with dynamic voltage scaling (DVS). We present a novel optimization formulation for minimizing average energy consumption while providing a probabilistic guarantee for satisfying timing constraints. We compare our stochastic models and energy management scheme with other models and schemes that do not capture/exploit either the variability of or the correlations among the computational loads of tasks.","PeriodicalId":119898,"journal":{"name":"3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005.","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122155917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-09-22DOI: 10.1109/ESTMED.2005.1518082
A. Özcan, O. Layaida, J. Stefani
Vis-a-vis the growing application complexity, embedded software developers are in search of novel design methodologies. Component-based software engineering seems to be a good candidate to respond to this need. We are developing Think, a light-weight implementation of Fractal components that is specially designed for embedded software systems. In this paper, we explain over an H.264 decoder case study how component-based design increases the software reuse, enables the specialization of the underlying system software and unifies the implementation with architectural design while ensuring high performance.
{"title":"A component-based approach for MPSoC SW design: experience with OS customization for H.264 decoder","authors":"A. Özcan, O. Layaida, J. Stefani","doi":"10.1109/ESTMED.2005.1518082","DOIUrl":"https://doi.org/10.1109/ESTMED.2005.1518082","url":null,"abstract":"Vis-a-vis the growing application complexity, embedded software developers are in search of novel design methodologies. Component-based software engineering seems to be a good candidate to respond to this need. We are developing Think, a light-weight implementation of Fractal components that is specially designed for embedded software systems. In this paper, we explain over an H.264 decoder case study how component-based design increases the software reuse, enables the specialization of the underlying system software and unifies the implementation with architectural design while ensuring high performance.","PeriodicalId":119898,"journal":{"name":"3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116719276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-09-22DOI: 10.1109/ESTMED.2005.1518063
Feng Liu, C. Tsui
Resolution scalable compression and power efficient channel decoder design are the enabling techniques for multi-resolution wireless multimedia broadcasting. In this paper, we propose a data-discarding framework which controls the switching of the Viterbi decoder between active and sleep mode for decoding multi-resolution JPEG2000 images to significantly reduce the overall power consumption of the channel decoder. In particular, the Viterbi decoder is put into sleep mode to skip the decoding of the redundant higher resolution data according to the results of the source decoding. The proposed framework is independent of the underlying communication channel and the architecture of the Viterbi decoder. Hence, it can be applied on top of any existing low-power Viterbi decoders to further reduce the overall power consumption. Our results show that up to 75% power reduction is achieved when the source resolution, the target resolution, and the compression ratio are 1024/spl times/1024, 256/spl times/256, and 1 bit/pixel (bpp), respectively.
{"title":"A data discarding framework for reducing the energy consumption of Viterbi decoder in decoding broadcasted wireless multi-resolution JPEG2000 images","authors":"Feng Liu, C. Tsui","doi":"10.1109/ESTMED.2005.1518063","DOIUrl":"https://doi.org/10.1109/ESTMED.2005.1518063","url":null,"abstract":"Resolution scalable compression and power efficient channel decoder design are the enabling techniques for multi-resolution wireless multimedia broadcasting. In this paper, we propose a data-discarding framework which controls the switching of the Viterbi decoder between active and sleep mode for decoding multi-resolution JPEG2000 images to significantly reduce the overall power consumption of the channel decoder. In particular, the Viterbi decoder is put into sleep mode to skip the decoding of the redundant higher resolution data according to the results of the source decoding. The proposed framework is independent of the underlying communication channel and the architecture of the Viterbi decoder. Hence, it can be applied on top of any existing low-power Viterbi decoders to further reduce the overall power consumption. Our results show that up to 75% power reduction is achieved when the source resolution, the target resolution, and the compression ratio are 1024/spl times/1024, 256/spl times/256, and 1 bit/pixel (bpp), respectively.","PeriodicalId":119898,"journal":{"name":"3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127970074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-09-22DOI: 10.1109/ESTMED.2005.1518055
K. Nahrstedt
Summary form only given. The tele-immersive 3D multi-camera room environments are starting to emerge in order to assist in distributed physical activities such as physical therapy, sport activities, and entertainment, and with them new challenging research questions. These environments need 3D multi-camera setups at the sending side and multi-display setups at the receiving side connected via appropriate network infrastructure. One important question is what is the next generation of system architectures that allow to build these environments in a flexible manner, with COTS components and for broader audience. In this paper we discuss challenges of system architectures as well as present possible solutions. We investigate the design space between the 3D multi-camera/multi-display tele-immersive edges and the general purpose computing and communication infrastructure available today. Especially, we analyze on our cross-layer control and streaming framework over general purpose delivery infrastructure, called TEEVE (tele-immersive environment for everybody), the difficulties and effectiveness of tele-immersive architectural constructs such as capturing, reconstructing and displaying 4D content, and coordination, synchronization and QoS-enabled delivery of tele-immersive 3D visual streams to remote room(s) over Internet 2. The first experiments of TEEVE and few other next generation architectures are encouraging, as we start to sustain communication of up to 12 3D streams with several frames per second (e.g., TEEVE can reach around 5 frames per second) over Internet 2, but a lot of work and challenges remain to be solved.
{"title":"Next generation of system architectures for tele-immersive environments","authors":"K. Nahrstedt","doi":"10.1109/ESTMED.2005.1518055","DOIUrl":"https://doi.org/10.1109/ESTMED.2005.1518055","url":null,"abstract":"Summary form only given. The tele-immersive 3D multi-camera room environments are starting to emerge in order to assist in distributed physical activities such as physical therapy, sport activities, and entertainment, and with them new challenging research questions. These environments need 3D multi-camera setups at the sending side and multi-display setups at the receiving side connected via appropriate network infrastructure. One important question is what is the next generation of system architectures that allow to build these environments in a flexible manner, with COTS components and for broader audience. In this paper we discuss challenges of system architectures as well as present possible solutions. We investigate the design space between the 3D multi-camera/multi-display tele-immersive edges and the general purpose computing and communication infrastructure available today. Especially, we analyze on our cross-layer control and streaming framework over general purpose delivery infrastructure, called TEEVE (tele-immersive environment for everybody), the difficulties and effectiveness of tele-immersive architectural constructs such as capturing, reconstructing and displaying 4D content, and coordination, synchronization and QoS-enabled delivery of tele-immersive 3D visual streams to remote room(s) over Internet 2. The first experiments of TEEVE and few other next generation architectures are encouraging, as we start to sustain communication of up to 12 3D streams with several frames per second (e.g., TEEVE can reach around 5 frames per second) over Internet 2, but a lot of work and challenges remain to be solved.","PeriodicalId":119898,"journal":{"name":"3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130551960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-09-22DOI: 10.1109/ESTMED.2005.1518084
G. Agosta, F. Bruschi, M. Santambrogio, D. Sciuto
The implementation technologies for electronic devices are experiencing a shift towards the use of reconfigurable devices. These devices are widely appreciated, especially in the design of embedded devices, since they allow to significantly lower the non-recurrent engineering costs associated with the hardware implementation of functionalities. In addition to these advantages, reconfigurable devices offer the possibility of implementing extremely flexible systems that can adapt or augment their hardware resources at run-time. To enable the exploitation of this important feature a key point is to make the designers able to model and validate reconfigurable systems, and to assist them in the evaluation of different target reconfigurable architectures. In this paper we address the problems of modeling configurability for streaming data decoding systems at a high level of abstraction, and of the subsequent synthesis on a reconfigurable device. In particular, we define an abstraction of a generic reconfigurable architecture based on elementary modular cells (reconfigurable architecture description layer, or RADL). To model and validate reconfigurable behaviors we defined a formalism that is based on the object-oriented features of Java and on its possibility to vary the class pool at run-time. We then formally address the problem of synthesizing such a high-level model upon the reconfigurable architecture abstraction defined. In order to explore the effectiveness of the model, we implemented a single RADL cell prototype and evaluated area cost and reconfiguration times.
{"title":"A data oriented approach to the design of reconfigurable stream decoders","authors":"G. Agosta, F. Bruschi, M. Santambrogio, D. Sciuto","doi":"10.1109/ESTMED.2005.1518084","DOIUrl":"https://doi.org/10.1109/ESTMED.2005.1518084","url":null,"abstract":"The implementation technologies for electronic devices are experiencing a shift towards the use of reconfigurable devices. These devices are widely appreciated, especially in the design of embedded devices, since they allow to significantly lower the non-recurrent engineering costs associated with the hardware implementation of functionalities. In addition to these advantages, reconfigurable devices offer the possibility of implementing extremely flexible systems that can adapt or augment their hardware resources at run-time. To enable the exploitation of this important feature a key point is to make the designers able to model and validate reconfigurable systems, and to assist them in the evaluation of different target reconfigurable architectures. In this paper we address the problems of modeling configurability for streaming data decoding systems at a high level of abstraction, and of the subsequent synthesis on a reconfigurable device. In particular, we define an abstraction of a generic reconfigurable architecture based on elementary modular cells (reconfigurable architecture description layer, or RADL). To model and validate reconfigurable behaviors we defined a formalism that is based on the object-oriented features of Java and on its possibility to vary the class pool at run-time. We then formally address the problem of synthesizing such a high-level model upon the reconfigurable architecture abstraction defined. In order to explore the effectiveness of the model, we implemented a single RADL cell prototype and evaluated area cost and reconfiguration times.","PeriodicalId":119898,"journal":{"name":"3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128765956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-09-22DOI: 10.1109/ESTMED.2005.1518081
A. Davare, Qi Zhu, J. Moondanos, A. Sangiovanni-Vincentelli
Multimedia systems are becoming increasingly complex and concurrent. The platform-based design (PBD) methodology (Keutzer et al., 2000) tackles these issues by recommending the use of formal models, carefully defined abstraction layers and the separation of concerns. Models of computation (Lee and Sangiovanni-Vincentelli, 1998) (MoCs) can be used within this methodology to enable specialized synthesis and verification techniques. In this paper, these concepts are leveraged in an industrial case study: the JPEG encoder application deployed on the Intel MXP5800 imaging processor. The modeling is carried out in the Metropolis (Balarin et al., 2003) design framework. We show that the system-level model using our chosen model of computation allows performance estimation within 5% of the actual implementation. Moreover, the chosen MoC is amenable to automation, which enables future synthesis techniques.
多媒体系统正变得越来越复杂和并行。基于平台的设计(PBD)方法(Keutzer et al.， 2000)通过推荐使用正式模型、仔细定义的抽象层和关注点分离来解决这些问题。计算模型(Lee和Sangiovanni-Vincentelli, 1998) (moc)可以在这种方法中使用，以实现专门的合成和验证技术。在本文中，在一个工业案例研究中利用了这些概念:部署在Intel MXP5800成像处理器上的JPEG编码器应用程序。建模在Metropolis (Balarin et al.， 2003)设计框架中进行。我们表明，使用我们选择的计算模型的系统级模型允许在实际实现的5%以内进行性能估计。此外，所选择的MoC可以自动化，这使得未来的合成技术成为可能。
{"title":"JPEG encoding on the Intel MXP5800: a platform-based design case study","authors":"A. Davare, Qi Zhu, J. Moondanos, A. Sangiovanni-Vincentelli","doi":"10.1109/ESTMED.2005.1518081","DOIUrl":"https://doi.org/10.1109/ESTMED.2005.1518081","url":null,"abstract":"Multimedia systems are becoming increasingly complex and concurrent. The platform-based design (PBD) methodology (Keutzer et al., 2000) tackles these issues by recommending the use of formal models, carefully defined abstraction layers and the separation of concerns. Models of computation (Lee and Sangiovanni-Vincentelli, 1998) (MoCs) can be used within this methodology to enable specialized synthesis and verification techniques. In this paper, these concepts are leveraged in an industrial case study: the JPEG encoder application deployed on the Intel MXP5800 imaging processor. The modeling is carried out in the Metropolis (Balarin et al., 2003) design framework. We show that the system-level model using our chosen model of computation allows performance estimation within 5% of the actual implementation. Moreover, the chosen MoC is amenable to automation, which enables future synthesis techniques.","PeriodicalId":119898,"journal":{"name":"3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114226257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-09-22DOI: 10.1109/ESTMED.2005.1518074
Qiu-Zhong Wu, Yi-He Sun
This paper presents an integrated computer aided design (CAD) tool for the ASIC implementation of multiplierless FIR digital filters with common sub-expression elimination (CSE) optimization. The main functions in the design flow of FIR filters for specified applications, including coefficient calculation and quantization, common sub-expression optimization and hardware description language (HDL) code auto-generation, are combined in this tool. We propose an applied intermedial representation (IR), which is the key for the integration of CSE optimization and HDL code auto-generation, to denote the circuit structure resulted from the application of CSE technique. The application of this tool in the ASIC implementation of multiplierless FIR filters can realize the design automation and shorten the time for design significantly; what is more, experiment results show that the desired FIR filters are optimized efficiently in several aspects such as area, power dissipation and speed.
{"title":"An integrated CAD tool for ASIC implementation of multiplierless FIR filters with common sub-expression elimination optimization","authors":"Qiu-Zhong Wu, Yi-He Sun","doi":"10.1109/ESTMED.2005.1518074","DOIUrl":"https://doi.org/10.1109/ESTMED.2005.1518074","url":null,"abstract":"This paper presents an integrated computer aided design (CAD) tool for the ASIC implementation of multiplierless FIR digital filters with common sub-expression elimination (CSE) optimization. The main functions in the design flow of FIR filters for specified applications, including coefficient calculation and quantization, common sub-expression optimization and hardware description language (HDL) code auto-generation, are combined in this tool. We propose an applied intermedial representation (IR), which is the key for the integration of CSE optimization and HDL code auto-generation, to denote the circuit structure resulted from the application of CSE technique. The application of this tool in the ASIC implementation of multiplierless FIR filters can realize the design automation and shorten the time for design significantly; what is more, experiment results show that the desired FIR filters are optimized efficiently in several aspects such as area, power dissipation and speed.","PeriodicalId":119898,"journal":{"name":"3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116762567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-09-22DOI: 10.1109/ESTMED.2005.1518069
T. Marescaux, B. Bricke, P. Debacker, V. Nollet, H. Corporaal
MP-SoCs are expected to require complex communication architectures such as NoCs. This paper presents, to our knowledge, the first algorithm to dynamically perform routing and allocation of guaranteed communication resources on NoCs that provide QoS with TDMA techniques. We test the efficiency of our algorithm by allocating the communication channels required for an application composed of a 3D pipeline and an MPEG-2 decoder/encoder video chain on a 16 node MP-SoC. Dynamism in the communication is created by the 3D application. On a StrongARM processor clocked at 200 MHz, the allocation time for one time-slot takes about 1000 cycles per hop in the connection. We show that central time-slot allocation algorithms are practical for small-scale MP-SoC systems. Indeed, our algorithm can compute the allocation of 40 connections for a complex scene of the 3D pipeline in 450 to 900 /spl mu/s, depending on the slot table size.
{"title":"Dynamic time-slot allocation for QoS enabled networks on chip","authors":"T. Marescaux, B. Bricke, P. Debacker, V. Nollet, H. Corporaal","doi":"10.1109/ESTMED.2005.1518069","DOIUrl":"https://doi.org/10.1109/ESTMED.2005.1518069","url":null,"abstract":"MP-SoCs are expected to require complex communication architectures such as NoCs. This paper presents, to our knowledge, the first algorithm to dynamically perform routing and allocation of guaranteed communication resources on NoCs that provide QoS with TDMA techniques. We test the efficiency of our algorithm by allocating the communication channels required for an application composed of a 3D pipeline and an MPEG-2 decoder/encoder video chain on a 16 node MP-SoC. Dynamism in the communication is created by the 3D application. On a StrongARM processor clocked at 200 MHz, the allocation time for one time-slot takes about 1000 cycles per hop in the connection. We show that central time-slot allocation algorithms are practical for small-scale MP-SoC systems. Indeed, our algorithm can compute the allocation of 40 connections for a complex scene of the 3D pipeline in 450 to 900 /spl mu/s, depending on the slot table size.","PeriodicalId":119898,"journal":{"name":"3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127801533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-09-22DOI: 10.1109/ESTMED.2005.1518083
Jeffrey Kang, T. Henriksson, P. V. D. Wolf
Embedded multimedia systems are becoming more complex and versatile, and need to support dynamic applications with multiple use cases. Switching from one use case to another during run time involves changing the application task graph configuration. This paper presents concepts and an interface for modeling and implementing dynamic applications. We show that this interface can be used to model several application change scenarios, and that it can be implemented on different multiprocessor architectures.
{"title":"An interface for the design and implementation of dynamic applications on multi-processor architectures","authors":"Jeffrey Kang, T. Henriksson, P. V. D. Wolf","doi":"10.1109/ESTMED.2005.1518083","DOIUrl":"https://doi.org/10.1109/ESTMED.2005.1518083","url":null,"abstract":"Embedded multimedia systems are becoming more complex and versatile, and need to support dynamic applications with multiple use cases. Switching from one use case to another during run time involves changing the application task graph configuration. This paper presents concepts and an interface for modeling and implementing dynamic applications. We show that this interface can be used to model several application change scenarios, and that it can be implemented on different multiprocessor architectures.","PeriodicalId":119898,"journal":{"name":"3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133978084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-09-22DOI: 10.1109/ESTMED.2005.1518087
Manish Verma, Klaus Petzold, L. Wehmeyer, H. Falk, P. Marwedel
Portable embedded systems require diligence in managing their energy consumption. Thus, power efficient processors coupled with onchip memories (e.g. caches, scratchpads) are the base of today's portable devices. Scratchpads are more energy efficient than caches but require software support for their utilization. Portable devices' applications consist of multiple processes for different tasks. However, all the previous scratchpad allocation approaches only consider single process applications. In this paper, we propose a set of optimal strategies to reduce the energy consumption of applications by sharing the scratchpad among multiple processes. The strategies assign both code and data elements to the scratchpad and result in average total energy reductions of 9%-20% against a published single process approach. Furthermore, the strategies generate Pareto-optimal curves for the applications allowing design time exploration of energy/scratchpad size tradeoffs.
{"title":"Scratchpad sharing strategies for multiprocess embedded systems: a first approach","authors":"Manish Verma, Klaus Petzold, L. Wehmeyer, H. Falk, P. Marwedel","doi":"10.1109/ESTMED.2005.1518087","DOIUrl":"https://doi.org/10.1109/ESTMED.2005.1518087","url":null,"abstract":"Portable embedded systems require diligence in managing their energy consumption. Thus, power efficient processors coupled with onchip memories (e.g. caches, scratchpads) are the base of today's portable devices. Scratchpads are more energy efficient than caches but require software support for their utilization. Portable devices' applications consist of multiple processes for different tasks. However, all the previous scratchpad allocation approaches only consider single process applications. In this paper, we propose a set of optimal strategies to reduce the energy consumption of applications by sharing the scratchpad among multiple processes. The strategies assign both code and data elements to the scratchpad and result in average total energy reductions of 9%-20% against a published single process approach. Furthermore, the strategies generate Pareto-optimal curves for the applications allowing design time exploration of energy/scratchpad size tradeoffs.","PeriodicalId":119898,"journal":{"name":"3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005.","volume":"PP 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126355010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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