How to design an input stage for neural recording system in 22 nm FDSOI

Abstract

The increase of recording channels in modern electrode-based neural recording systems is limited by considerations of power. Emerging CMOS technologies like 22 nm FDSOI promise to open new perspectives in overcoming power constraints due to their particular energy efficiency in digital circuit integration, they however also pose a challenge for the analogue front-end stages of such systems, especially with respect to signal noise. This paper addresses the design of low noise amplifiers (LNA), the most critical component with respect to power and noise, in this technology and application. Moreover, a trade-off between igs-shot noise and flicker noise is described, which leads to the design of the LNA’s operational amplifier, minimising noise for a given current. Capacitor types vary in leakage and hence in noise. We therefore simulated and analysed different types and sizes of DC-decoupling capacitors for an estimation of the minimum-area requirement of the LNA. Notably, the described design approaches the minimum input-referred noise possible for a given current and input capacitor in this technology.