{"title":"An avoidance technique for mitigating the integer boundary spur problem in a DDS-PLL hybrid frequency synthesizer","authors":"R. Vishnu, S. S. Anulal","doi":"10.1109/ICCSP.2015.7322927","DOIUrl":null,"url":null,"abstract":"Modem frequency hopping radios makes use of Direct Digital Synthesis (DDS) - Phase Locked Loop (PLL) hybrid architecture based frequency synthesizers. The advantage is the fast switching speed and fine tuning resolution of the DDS, complemented with very low phase noise and spurious performance of the PLL. Integer boundary spur is a problem area, which restrict the spurious performance of the DDS-PLL translation loop. An algorithm was developed which identifies whether the tuned frequency is prone to integer boundary spurs. If it is, then the DDS and PLL frequencies are configured such that the generated spurs are outside the loop filter bandwidth, so that they are attenuated by the loop. The algorithm runs as a sub-routine in the micro-controller which programs the DDS and PLL. This algorithm was developed and tested on a wideband frequency synthesizer operating from 600-1200MHz, albeit the method is independent of frequency of operation.","PeriodicalId":174192,"journal":{"name":"2015 International Conference on Communications and Signal Processing (ICCSP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 International Conference on Communications and Signal Processing (ICCSP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCSP.2015.7322927","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
Modem frequency hopping radios makes use of Direct Digital Synthesis (DDS) - Phase Locked Loop (PLL) hybrid architecture based frequency synthesizers. The advantage is the fast switching speed and fine tuning resolution of the DDS, complemented with very low phase noise and spurious performance of the PLL. Integer boundary spur is a problem area, which restrict the spurious performance of the DDS-PLL translation loop. An algorithm was developed which identifies whether the tuned frequency is prone to integer boundary spurs. If it is, then the DDS and PLL frequencies are configured such that the generated spurs are outside the loop filter bandwidth, so that they are attenuated by the loop. The algorithm runs as a sub-routine in the micro-controller which programs the DDS and PLL. This algorithm was developed and tested on a wideband frequency synthesizer operating from 600-1200MHz, albeit the method is independent of frequency of operation.