An On-Chip Interpolation Based Readout Scheme for Low-Power, High-Speed CMOS Image Sensors

Abstract

A low-power, high-speed on-chip compression and reconstruction technique is proposed in this paper. It takes the advantage of correlation between the consecutive pixels and reduces the total number of pixels to be read. The discarded pixels are interpolated on-chip using the proposed interpolation circuit. This reduces the total number of A/D conversions and hence results in power saving. The algorithm is verified for standard Lena image and about 5 dB better PSNR is observed for 20%- 90% compression, as compared to the existing techniques. Moreover, a promising performance is achieved on thermal image applications. The circuit is designed and simulated in AMS 350 nm OPTO process. For 57% compression, about 45% power saving in readout of the image sensor is observed.