A Simulation and Experimental Study of Input Decoupled Partially Adiabatic Logic (IDPAL)

Abstract

Input decoupled partially adiabatic logic (IDPAL) is a recent adiabatic logic circuit technology that features a switching network separated from the buffer portion of the logic gate. The original formulation of IDPAL showed performance degradation at higher operational frequencies. As a result, a refinement is introduced, IDPAL with discharge, that performs at speeds comparable to other adiabatic technologies. Reported here is the first experimental study of an IDPAL circuit implementation. The circuit studied is an eight-input exclusive-OR gate organized into three layers of logic. Both IDPAL and IDPAL with discharge are studied and compared with efficient charge recovery logic (ECRL). Notably, IDPAL with discharge was shown to operate without degradation at frequencies comparable to ECRL.