Performance evaluation of 7nm n-type germanium junctionless field-effect-transistor with metal-interlayer-semiconductor source/drain structure

Abstract

In this study, the impact of Metal-Interlayer-Semiconductor Source/Drain (MIS S/D) structure on enhancement mode 7nm n-type germanium (Ge) junctionless FET (JLFET) is demonstrated with Sentaurus 3-D technology computer-aided design (TCAD). The device using MS S/D structure cannot operate for normally-off mode because of severe Fermi-level pinning (FLP) and using MIS S/D structure can be a solution by alleviating the FLP. We compared performances of the normally-off JLFET models which include MIS S/D, conventional metal-semiconductor S/D (MS S/D) and unpinned metal-semiconductor S/D (unpinned MS S/D) structures. The MIS S/D structure provides on-state current of 6.09 × 10−4 A/um and contact resistivity of 3 × 10−9Ω-cm2. We also analyzed the MIS S/D JLFET by different doping concentrations.