Fault Tolerant Architecture Design of a 4-bit Magnitude Comparator

Abstract

This paper provides a detailed explanation of a fault tolerant method to provide uninterrupted operation in a magnitude comparator based system. Fault may manifest in an electronic system either by virtue of external or internal factors. The following structure provides a subtle way to minimize those factors and make a 4-bit fault tolerant magnitude comparator so that it can reconfigure itself automatically. Area overheard, delay and cost efficiency of our proposed method is compared to that of Triple Modular Redundancy's.