The Study of Bit Line to Storage Node Contact Leakage in Advanced DRAM

Abstract

Retention time is a critical characteristic in Dynamic Random Memory (DRAM). In order to improve DRAM retention time, leakage must be reduced. In manufacturing, the bit line (BL) to storage Node Contact (NC) leakage is one of a key charge leak path. In this paper, BL and NC structure in an advanced 1y DRAM process were modeled and analyzed using the virtual fabrication platform. The BL overlay shifts and NC critical dimension (CD) enlarge effects on BL-NC leakage performance has been studied with direct tunneling simulation. Our analysis confirmed that the BL-NC leakage worse induced by BL footing and NC bottom damage and proper specification can be suggested to avoid such issue.