A low leakage poly-gated SCR device for ESD protection in 65nm CMOS process

Abstract

A low-leakage, low triggering polysilicon bounded SCR design is introduced for on-chip electrostatic discharge (ESD) protection in CMOS applications. The advantages of replacing the shallow trench isolation (STI) with a polysilicon gate in the device formation are discussed. The device response to fast transients, emulating ESD CDM-type events, is discussed through VFTLP measurements. The low-leakage characteristics of the SCR clamp are also demonstrated via high temperature measurements.