Efficient PEEC-based inductance extraction using circuit-aware techniques

Abstract

Practical approaches for on-chip inductance extraction to obtain a sparse, stable and accurate inverse inductance matrix K are proposed. The novelty of our work is in using circuit characteristics to define the concept of resistance-dominant and inductance-dominant lines. This notion is used to progressively refine a set of clusters that are inductively tightly-coupled. For reasonable designs, the more exact algorithm yields a sparsification of 97% for delay and oscillation magnitude errors of 10% and 15%, respectively, while the more approximate algorithm achieves up to 99% sparsification. An offshoot of this work is K-PRIMA, an extension of PRIMA to handle K matrices with guaranteed passivity.