Physical Design and Verification for Embedded CPU under Deep Submicron Technology

Abstract

To overcome the challenges brought by the scale down of feature size, a flow of physical design and verification for embedded CPU under deep submicron technology is put forward in this paper. New problems are encountered in timing closure, signal integrity, IR drop and antenna effect, so we must select the effective EDA tools and develop new flow of physical design and verification combining with the characteristics of circuit under deep submicron technology. New challenges are analyzed, especially the interconnect line effect, and how to prevent the crosstalk and ensure the timing performance has been discussed. The embedded CPU CK610 using 0.13um 1P4M CMOS process technology has been completed by this new flow and the result indicates this chip complies with all requirements.