Finfet Standard Cells Delay Model for Fast Timing Analysis

Abstract

The fast growth of the real projects on FinFET technology has led to the need of design flow changes at all levels of abstraction. Especially interesting for designers is the possibility of early exploration of the FinFET standard cells timings. In this case, it is necessary to take into account the quantification of FinFET channel width, determined by an integer number of fins. The paper presents a model for standard cell delay calculation, which can be used for quick analysis of design options. The linear model allows to calculate the critical path in the circuit without full circuit simulation, using only a small number of empirical parameters. An example of development such model for 20 nm technology is given in the paper.