On cycle borrowing analyses for interconnected chips driven by clocks having different but commensurable speeds

G. Jennings
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引用次数: 3

Abstract

The author considers the construction of synchronous systems having components driven at different rates by different, but commensurable, clocks. Furthermore these systems are to be constructed using level-sensitive latches with the intent of exploiting cycle borrowing over the entire system. The author presents a framework in which the entire system is managed as a single clocked entity, and investigates a timing analysis technique for such systems. Results for small examples are presented. The interface between such chips is studied; no resynchronizers are required. Alternate clock waveforms, and their effect on analysis complexity, are discussed.<>
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由不同但可通约的时钟驱动的互连芯片的周期借用分析
作者考虑了具有由不同但可通约的时钟以不同速率驱动的组件的同步系统的构造。此外,这些系统将使用电平敏感锁存器构建,目的是利用整个系统的周期借用。作者提出了一个框架,在这个框架中,整个系统作为一个单一的时钟实体来管理,并研究了这种系统的时序分析技术。给出了小实例的结果。研究了这些芯片之间的接口;不需要重新同步器。讨论了交替时钟波形及其对分析复杂度的影响。
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