Vacuum Reflow Process Characterization for Void-Less Soldering Process in Semiconductor Package

Abstract

Semiconductor packaging's solder void criteria is getting tighter overtime due to involvement of high usage in automotive industry. Semiconductor packaging component maker starts to strengthen the solder joint quality and electrical power conductivity by tighten the solder void requirement through seeking a solution in controlling the maximum solder void size reduction from 10-15% original fraction to 5% or below over die size. Vacuum reflow is introduced to overcome this challenge. Critical process parameters in vacuum reflow process including temperature and pressure were characterized for void reduction and compared to that of conventional reflow process. Promising results show that high temperature, fast depressurize rate and long pressure dwell time in low pressurized environment as well as solder paste volume increment are critical factors in providing minimum solder void sizes that successfully meet the new industry criteria.