Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511678
Ibn'Asyura Zainuddin
Tape dicing concept is most commonly used in miniature QFN package singulation process due to its low operating cost and high throughput [1]. Processing with strip based material, starting from saw singulation to unit transfer into reel tape, while sawn unit still intact on dicing tape, robust process is needed as well as short cycle time for productivity. Currently, there are 2 common tape dicing methods. Firstly, strip cutting method, and secondly, strip to panel cutting method [2]. Both methods have pros & cons respectively. Nevertheless, in order to improve cycle time, extreme processing method is needed without jeopardizing the processing quality. Introducing this strip chopping cut method enables singulation process of maximum unit density per 12 inches wafer ring and processing abnormal lead frame design with thick metal side rail and moulded-only layer on panel. This method needs dicing blade to directly touch down on top of moulded package during cutting without fully cut metal side rail. In this paper, will further discuss in details how it works and what are the pros and cons, as well as its benefits.
{"title":"An Introduction of Strip Chopping Cut Method to Establish a Robust Strip Based Dicing Process on Tape Dicing Concept","authors":"Ibn'Asyura Zainuddin","doi":"10.1109/IEMT.2018.8511678","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511678","url":null,"abstract":"Tape dicing concept is most commonly used in miniature QFN package singulation process due to its low operating cost and high throughput [1]. Processing with strip based material, starting from saw singulation to unit transfer into reel tape, while sawn unit still intact on dicing tape, robust process is needed as well as short cycle time for productivity. Currently, there are 2 common tape dicing methods. Firstly, strip cutting method, and secondly, strip to panel cutting method [2]. Both methods have pros & cons respectively. Nevertheless, in order to improve cycle time, extreme processing method is needed without jeopardizing the processing quality. Introducing this strip chopping cut method enables singulation process of maximum unit density per 12 inches wafer ring and processing abnormal lead frame design with thick metal side rail and moulded-only layer on panel. This method needs dicing blade to directly touch down on top of moulded package during cutting without fully cut metal side rail. In this paper, will further discuss in details how it works and what are the pros and cons, as well as its benefits.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116933370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511798
Eric Wong Soon Kiong, C. Y. Lai
Scanning acoustic microcopy (SAM) method with inverted inspection direction has been successfully develop and evaluate the quality of flip chip underfill and interconnect bonds in manufacturing of microelectronic components. Acoustic microscopes utilize high frequency ultrasound transmitting through the silicon chip backside in one scan to access and examine the internal structures in optically opaque materials. These non-destructive methods relatively enable the defect localization which leads microstructural examinations involving destructive analysis sample preparation. For the justification of accuracy of SAM method analysis, a destructive cross-sectioned and mechanical lapping physical analysis were performed for preparing the samples and examine by optical microscope and Scanning Electron Microscope (SEM) for defect verification. Cases studies have been demonstrated that the capabilities of conventional SAM inspection and advantages over other analysis method.
{"title":"Assessment Methodology on Mold Void Defect by Scanning Acoustic Microscopy (SAM) Non-Destructive Technique","authors":"Eric Wong Soon Kiong, C. Y. Lai","doi":"10.1109/IEMT.2018.8511798","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511798","url":null,"abstract":"Scanning acoustic microcopy (SAM) method with inverted inspection direction has been successfully develop and evaluate the quality of flip chip underfill and interconnect bonds in manufacturing of microelectronic components. Acoustic microscopes utilize high frequency ultrasound transmitting through the silicon chip backside in one scan to access and examine the internal structures in optically opaque materials. These non-destructive methods relatively enable the defect localization which leads microstructural examinations involving destructive analysis sample preparation. For the justification of accuracy of SAM method analysis, a destructive cross-sectioned and mechanical lapping physical analysis were performed for preparing the samples and examine by optical microscope and Scanning Electron Microscope (SEM) for defect verification. Cases studies have been demonstrated that the capabilities of conventional SAM inspection and advantages over other analysis method.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127250814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511717
Wai-Hau Ng, Yang-Hong Lee, E. Lim, B. Chung
A UHF RFID wristband tag is designed using a planar inverted-F antenna (PIFA). With the use of the folding technique and the PP-2 soft foam substrate, the tag can be made compact, light-weight, and flexible for electronic package. The tag's footprint is only 900 mm2 with almost 100% power transmission. From simulation, the wristband tag has a theoretical read range of 8.3 m at 923 MHz when placed on a rectangular phantom. With a 3.28 W EIRP, it is also experimentally demonstrated that the wristband tag can be read from 5.1 m when it is tested on minced meat.
{"title":"Design of a Compact PIFA Tag Antenna for Wearable Electronics","authors":"Wai-Hau Ng, Yang-Hong Lee, E. Lim, B. Chung","doi":"10.1109/IEMT.2018.8511717","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511717","url":null,"abstract":"A UHF RFID wristband tag is designed using a planar inverted-F antenna (PIFA). With the use of the folding technique and the PP-2 soft foam substrate, the tag can be made compact, light-weight, and flexible for electronic package. The tag's footprint is only 900 mm2 with almost 100% power transmission. From simulation, the wristband tag has a theoretical read range of 8.3 m at 923 MHz when placed on a rectangular phantom. With a 3.28 W EIRP, it is also experimentally demonstrated that the wristband tag can be read from 5.1 m when it is tested on minced meat.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124358148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511797
C. Chiew, Paing Samsun, L. Vigneswaran, A. Ang
There are many QFN packaged ICs with different die pad design widely used in semiconductor industry. With minimum delta on die pad size and chip size ratio, this will continue maximize the package functionality in same package size, yet attractive cost packaged ICs. However, a different die pad size to chip ratio lead to different stress level to building part which resulted different delamination level in package. Not to miss out the stress created by manufacturing process with its tool construction which cause delamination to package in addition. In general, there are 2 types of stress; tensile stress and shear stress. It is easy to tackle the stress related delamination to mechanical faulty compare to thermal induced stress. The root cause of thermal induced stress may involve more than one heat treatment's processes imposed on ICs manufacturing line. A change of package design or bill of material (BOM) may be incurred to overcome the delamination due to thermal resulted stress. In this paper, a thermal simulation was carried out firstly on affected package design impacted with die pad delamination. The result confirms that high thermal stress was localised on affected die pad area with addition high warpage observed. This was lead to improvement activities on warpage, which was caused by different heat treatment process. A statistical study on warpage behaviour was conducted to different heat treatment process (die bonded, wire bonded and mold process). Result showed that die pad delamination was related to high heat treatment process at die attached process. To prove the failure mechanism, different heat treatment temperature on die attached was statistically studied. Data was proven that die pad delamination eliminated by low heat temperature in die attached process. To make a success on die pad delamination elimination, a replacement from solder paste to glue material (same CTE as solder paste) is required during die attached process with low heat treatment temperature. After building part, glue designed into package with die attached process characterization, no die pad delamination found. With the big scale production confirmation, low heat temperature at die attached process is a proven solution on die pad delamination in success for affected package.
{"title":"Die Pad Delamination on QFN Package","authors":"C. Chiew, Paing Samsun, L. Vigneswaran, A. Ang","doi":"10.1109/IEMT.2018.8511797","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511797","url":null,"abstract":"There are many QFN packaged ICs with different die pad design widely used in semiconductor industry. With minimum delta on die pad size and chip size ratio, this will continue maximize the package functionality in same package size, yet attractive cost packaged ICs. However, a different die pad size to chip ratio lead to different stress level to building part which resulted different delamination level in package. Not to miss out the stress created by manufacturing process with its tool construction which cause delamination to package in addition. In general, there are 2 types of stress; tensile stress and shear stress. It is easy to tackle the stress related delamination to mechanical faulty compare to thermal induced stress. The root cause of thermal induced stress may involve more than one heat treatment's processes imposed on ICs manufacturing line. A change of package design or bill of material (BOM) may be incurred to overcome the delamination due to thermal resulted stress. In this paper, a thermal simulation was carried out firstly on affected package design impacted with die pad delamination. The result confirms that high thermal stress was localised on affected die pad area with addition high warpage observed. This was lead to improvement activities on warpage, which was caused by different heat treatment process. A statistical study on warpage behaviour was conducted to different heat treatment process (die bonded, wire bonded and mold process). Result showed that die pad delamination was related to high heat treatment process at die attached process. To prove the failure mechanism, different heat treatment temperature on die attached was statistically studied. Data was proven that die pad delamination eliminated by low heat temperature in die attached process. To make a success on die pad delamination elimination, a replacement from solder paste to glue material (same CTE as solder paste) is required during die attached process with low heat treatment temperature. After building part, glue designed into package with die attached process characterization, no die pad delamination found. With the big scale production confirmation, low heat temperature at die attached process is a proven solution on die pad delamination in success for affected package.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128658405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511792
A. Denoyo, Rod J. Delos Santos, T. Pinili, Darwin J. De Lazo, Ivan T. Gil Costa, Allen M. Menor
In response to the need in the semiconductor industry to have a higher moisture sensitivity level (MSL) satisfying the no delamination criteria in all interfaces for automotive devices with a reasonable cost are the main objectives in this study. To attain these tasks, knowledge of the material components and a system in the evaluation process are the key to the success of this program. Different evaluation stages were initially defined and executed depending on bill-of-material (BOM) combination and complexities. Activities will also include process refinement, material selection, leadframe design improvement and surface enhancements. Initially, all existing critical process parameter conditions were identified and optimized to ensure a delamination-free package at time zero or after assembly after which moisture soaking is done at different conditions to identify and verify MSL capability. Once found incapable for no-delamination criteria, the change in mold compound material, leadframe design enhancement, and surface roughening will be introduced. For an SOIC package with the biggest silicon die and paddle size identified as the initial qualification test vehicle using a bare copper with spot silver type of leadframe, it was found out that with the optimized process parameter conditions and with the right mold compound can already achieve MSL 1 and even after 500 temperature cycles without any form of delamination in all regions - no need for further leadframe design enhancements, surface roughening treatments and additional process for surface activation. With this result on this specific package type, additional cost adders were avoided. Likewise, this solution will be extended to other package types with different surface finish for Pre-Plated Frames (PPFs) or Nickel-Palladium-Gold (NiPdAu) to check for process consistency and material compatibility.
{"title":"An Alternative Packaging Solution in Achieving Moisture Sensitivity Level One (1) for Small Outline Integrated Circuit (SOIC) Automotive Packages","authors":"A. Denoyo, Rod J. Delos Santos, T. Pinili, Darwin J. De Lazo, Ivan T. Gil Costa, Allen M. Menor","doi":"10.1109/IEMT.2018.8511792","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511792","url":null,"abstract":"In response to the need in the semiconductor industry to have a higher moisture sensitivity level (MSL) satisfying the no delamination criteria in all interfaces for automotive devices with a reasonable cost are the main objectives in this study. To attain these tasks, knowledge of the material components and a system in the evaluation process are the key to the success of this program. Different evaluation stages were initially defined and executed depending on bill-of-material (BOM) combination and complexities. Activities will also include process refinement, material selection, leadframe design improvement and surface enhancements. Initially, all existing critical process parameter conditions were identified and optimized to ensure a delamination-free package at time zero or after assembly after which moisture soaking is done at different conditions to identify and verify MSL capability. Once found incapable for no-delamination criteria, the change in mold compound material, leadframe design enhancement, and surface roughening will be introduced. For an SOIC package with the biggest silicon die and paddle size identified as the initial qualification test vehicle using a bare copper with spot silver type of leadframe, it was found out that with the optimized process parameter conditions and with the right mold compound can already achieve MSL 1 and even after 500 temperature cycles without any form of delamination in all regions - no need for further leadframe design enhancements, surface roughening treatments and additional process for surface activation. With this result on this specific package type, additional cost adders were avoided. Likewise, this solution will be extended to other package types with different surface finish for Pre-Plated Frames (PPFs) or Nickel-Palladium-Gold (NiPdAu) to check for process consistency and material compatibility.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129169683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Semiconductor packaging's solder void criteria is getting tighter overtime due to involvement of high usage in automotive industry. Semiconductor packaging component maker starts to strengthen the solder joint quality and electrical power conductivity by tighten the solder void requirement through seeking a solution in controlling the maximum solder void size reduction from 10-15% original fraction to 5% or below over die size. Vacuum reflow is introduced to overcome this challenge. Critical process parameters in vacuum reflow process including temperature and pressure were characterized for void reduction and compared to that of conventional reflow process. Promising results show that high temperature, fast depressurize rate and long pressure dwell time in low pressurized environment as well as solder paste volume increment are critical factors in providing minimum solder void sizes that successfully meet the new industry criteria.
{"title":"Vacuum Reflow Process Characterization for Void-Less Soldering Process in Semiconductor Package","authors":"Siang Miang Yeo, Azman Mahmood, Shahrul Haizal Ishak","doi":"10.1109/IEMT.2018.8511767","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511767","url":null,"abstract":"Semiconductor packaging's solder void criteria is getting tighter overtime due to involvement of high usage in automotive industry. Semiconductor packaging component maker starts to strengthen the solder joint quality and electrical power conductivity by tighten the solder void requirement through seeking a solution in controlling the maximum solder void size reduction from 10-15% original fraction to 5% or below over die size. Vacuum reflow is introduced to overcome this challenge. Critical process parameters in vacuum reflow process including temperature and pressure were characterized for void reduction and compared to that of conventional reflow process. Promising results show that high temperature, fast depressurize rate and long pressure dwell time in low pressurized environment as well as solder paste volume increment are critical factors in providing minimum solder void sizes that successfully meet the new industry criteria.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131039614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511656
M. Sharif, A. Saad, M. K. Abdullah, N. A. Aziz, N. A. Ismail
Advance of knowledge in material engineering has introduced stretchable electronic materials which can be stretched, bended or twisted and it is beneficial for consumer product manufacturing. This paper aims to study the effect of process combination of standard printing process in surface mount technology and thermoforming process on a stretchable conductive polymer to form a 3-dimensional electronic device. The polymer comprised of silver particles as fillers was prepared to produce a conductive and stretchable behavior which can withstand high temperature deformation. It was printed on a flat substrate using a screen printing technique and then being thermoformed to produce 3-dimensional shape of automotive rear lighting. Mechanical and electrical performances of the thermoformed product were characterized before and after thermoforming process to study the reliability of LEDs assembly with stretchable circuits. Four point probes instrument was used to measure resistivity of the printed circuit which was elongated due to thermoforming process. The elongation of circuit varied throughout the lighting prototype depending on complex geometry of mould. Conductivity of the circuit was also tested by LEDs illumination. Results of microscopy investigation, x-ray imaging and thermal cycling show good performances of LEDs joints. This new manufacturing process of printed circuit offers a promising future alternative method in manufacturing of 3dimensional electronic device. Keywords— Conductive polymer; printed electronics; thermoforming
{"title":"A study on a stretchable conductive polymer of thermoplastic automotive device","authors":"M. Sharif, A. Saad, M. K. Abdullah, N. A. Aziz, N. A. Ismail","doi":"10.1109/IEMT.2018.8511656","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511656","url":null,"abstract":"Advance of knowledge in material engineering has introduced stretchable electronic materials which can be stretched, bended or twisted and it is beneficial for consumer product manufacturing. This paper aims to study the effect of process combination of standard printing process in surface mount technology and thermoforming process on a stretchable conductive polymer to form a 3-dimensional electronic device. The polymer comprised of silver particles as fillers was prepared to produce a conductive and stretchable behavior which can withstand high temperature deformation. It was printed on a flat substrate using a screen printing technique and then being thermoformed to produce 3-dimensional shape of automotive rear lighting. Mechanical and electrical performances of the thermoformed product were characterized before and after thermoforming process to study the reliability of LEDs assembly with stretchable circuits. Four point probes instrument was used to measure resistivity of the printed circuit which was elongated due to thermoforming process. The elongation of circuit varied throughout the lighting prototype depending on complex geometry of mould. Conductivity of the circuit was also tested by LEDs illumination. Results of microscopy investigation, x-ray imaging and thermal cycling show good performances of LEDs joints. This new manufacturing process of printed circuit offers a promising future alternative method in manufacturing of 3dimensional electronic device. Keywords— Conductive polymer; printed electronics; thermoforming","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127599313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511790
Sim Jui Oon, K. S. Tan, T. Tou, S. Yap, C. Lau, Y. T. Chin
The demand for lightweight and high functionality devices is always a driving force in development of smaller, lighter and compact electronics circuit. Printed circuit board (PCB) is the most important structure that provides interconnection and supports the components; hence its flatness is always the main concern in SMT manufacturing. In order to ensure product reliability, the monitoring of thermally induced warpage of PCB during high temperature reflow is essential. PCB deformation occurs when there is mismatch of coefficients of thermal expansion between the materials. Thermally induced warpage in PCB can be obtained from the Shadow Moiré measurement, which is a non-contact full-field optical method integrated with a high temperature oven. In this study, a single-sided, small PCB (105 mm X 100 mm X 1.5 mm) and a large, multi-layer PCB (300 mm X 180 mm X 1.6 mm) are measured and analyzed. To reduce the temperature difference between the top and bottom of the PCBs, a heating profile is designed with the use of multiple thermocouples at various positions on the PCB. In addition, finite element analysis is carried out to determine the z-axis deformation of the PCBs. The finite-element simulation is setup to mimic the heating profile in the experiment. The results of simulation are compared to the experimental measurement.
对轻量化和高功能器件的需求一直是推动更小、更轻、更紧凑电子电路发展的动力。印刷电路板(PCB)是提供互连和支持组件的最重要的结构;因此，其平面度一直是SMT制造的主要关注点。为了保证产品的可靠性，对PCB在高温回流过程中的热致翘曲进行监测是十分必要的。当材料之间的热膨胀系数不匹配时，PCB板就会发生变形。阴影莫尔测量是一种与高温烘箱相结合的非接触式全场光学测量方法，可以获得PCB中的热致翘曲。在本研究中，测量和分析了单面小型PCB (105 mm X 100 mm X 1.5 mm)和大型多层PCB (300 mm X 180 mm X 1.6 mm)。为了减少PCB顶部和底部之间的温差，在PCB上的不同位置使用多个热电偶设计了加热剖面。此外，还进行了有限元分析，确定了pcb板的z轴变形。建立了模拟实验中加热剖面的有限元模拟。仿真结果与实验测量结果进行了比较。
{"title":"Warpage Studies of Printed Circuit Boards with Shadow Moiré and Simulations","authors":"Sim Jui Oon, K. S. Tan, T. Tou, S. Yap, C. Lau, Y. T. Chin","doi":"10.1109/IEMT.2018.8511790","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511790","url":null,"abstract":"The demand for lightweight and high functionality devices is always a driving force in development of smaller, lighter and compact electronics circuit. Printed circuit board (PCB) is the most important structure that provides interconnection and supports the components; hence its flatness is always the main concern in SMT manufacturing. In order to ensure product reliability, the monitoring of thermally induced warpage of PCB during high temperature reflow is essential. PCB deformation occurs when there is mismatch of coefficients of thermal expansion between the materials. Thermally induced warpage in PCB can be obtained from the Shadow Moiré measurement, which is a non-contact full-field optical method integrated with a high temperature oven. In this study, a single-sided, small PCB (105 mm X 100 mm X 1.5 mm) and a large, multi-layer PCB (300 mm X 180 mm X 1.6 mm) are measured and analyzed. To reduce the temperature difference between the top and bottom of the PCBs, a heating profile is designed with the use of multiple thermocouples at various positions on the PCB. In addition, finite element analysis is carried out to determine the z-axis deformation of the PCBs. The finite-element simulation is setup to mimic the heating profile in the experiment. The results of simulation are compared to the experimental measurement.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132792519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511708
Y. Chiew, J. Liong, F. Tan
The continuing package miniaturized on semiconductor industry had driven toward smaller feature sizes and higher density which will raise the hurdle of dicing. This has become a trend to increase the number of potential die per wafer (PDPW) by shrinking the saw street width to have a competitive product cost and strategically maintain the product margin that affected by yearly Average Selling Price (ASP) erosion. Producing a wafer is a fixed cost thus the more die per wafer equates to lower cost per die. Each die is separated from its neighbors by narrow saw street, which are the cut lines for singulating the die. The narrower saw street width, the more dies per wafer and the more challenging the dicing. Generally, the width of the saw streets has been reduced from former industry standard of 85um to 60um and now to latest 50um. The dicing challenges and quality issue become more crucial with the requirement of wafer backside coating (WBC), smaller die size, thinner wafer with passivation stacks on the saw street and existing of process control monitor (PCM) areas which contains the massive test structures. Key dicing quality characteristics focused in this paper are including top side chipping, passivation peeling and die side wall damage. This is most severe issue in dicing process and has induced the quality risk of customer return due to not easy or impossible to screen out at final test for those minor chipped/cracked die. Qualitative analysis will be carried out and high power microscope will be used to check for chipping condition or other defects. This paper reports the challenges faced and the successful development of 50um narrow saw street with conductive and nonconductive wafer backside coating on various thickness of wafers with six sigma process capability dicing performance and passed all the reliability stress test requirements. A comprehensive study was performed in optimizing critical dicing parameter such as blade height, suitable dicing blade and dicing tape.
{"title":"Mechanical Dicing Challenges and Development on 50um Saw Street with Wafer Backside Coating (WBC)","authors":"Y. Chiew, J. Liong, F. Tan","doi":"10.1109/IEMT.2018.8511708","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511708","url":null,"abstract":"The continuing package miniaturized on semiconductor industry had driven toward smaller feature sizes and higher density which will raise the hurdle of dicing. This has become a trend to increase the number of potential die per wafer (PDPW) by shrinking the saw street width to have a competitive product cost and strategically maintain the product margin that affected by yearly Average Selling Price (ASP) erosion. Producing a wafer is a fixed cost thus the more die per wafer equates to lower cost per die. Each die is separated from its neighbors by narrow saw street, which are the cut lines for singulating the die. The narrower saw street width, the more dies per wafer and the more challenging the dicing. Generally, the width of the saw streets has been reduced from former industry standard of 85um to 60um and now to latest 50um. The dicing challenges and quality issue become more crucial with the requirement of wafer backside coating (WBC), smaller die size, thinner wafer with passivation stacks on the saw street and existing of process control monitor (PCM) areas which contains the massive test structures. Key dicing quality characteristics focused in this paper are including top side chipping, passivation peeling and die side wall damage. This is most severe issue in dicing process and has induced the quality risk of customer return due to not easy or impossible to screen out at final test for those minor chipped/cracked die. Qualitative analysis will be carried out and high power microscope will be used to check for chipping condition or other defects. This paper reports the challenges faced and the successful development of 50um narrow saw street with conductive and nonconductive wafer backside coating on various thickness of wafers with six sigma process capability dicing performance and passed all the reliability stress test requirements. A comprehensive study was performed in optimizing critical dicing parameter such as blade height, suitable dicing blade and dicing tape.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116945009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511764
Lai Chin Yung, Ho Ing Hong, Eric Wong Soon Kiong, C. C. Fei
In recent years, flip chip packaging by application of a copper pillar bump as an interconnector within the packages has successfully shrunk the package size to a minimum level, by maintaining or maximizing the chip application functionality. Nevertheless, some weaknesses have been observed during the formation of solder joint connection between the copper pillars to die pad substrates. The most common defect, which is solder void formation at the solder joint area, will reduce the interconnection strength or robustness of the solder joint. To understand the solder void formation mechanism, a simulation experiment has been carried out by using copper and silver plated lead pad substrate for pillar solder joint formation process at different stress time interval. An analytical analysis by using 3D CT-scan has been carried out to detect the submicron size solder void defect, especially during high-temperature stress process. An elemental analysis by energy dispersive X-ray also has been carrying out to prove the substrate pad material dissolution mechanism during solder joint formation. With the experiment finding and deeply understanding the material dissolution behavior in packaging concept, this can ensure more robust pillar joint die bond process and guarantee quality packages built.
{"title":"Investigation on Solder Void Formation Mechanism After High Temperatures Stress by 3D CT Scan and EDX Analysis","authors":"Lai Chin Yung, Ho Ing Hong, Eric Wong Soon Kiong, C. C. Fei","doi":"10.1109/IEMT.2018.8511764","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511764","url":null,"abstract":"In recent years, flip chip packaging by application of a copper pillar bump as an interconnector within the packages has successfully shrunk the package size to a minimum level, by maintaining or maximizing the chip application functionality. Nevertheless, some weaknesses have been observed during the formation of solder joint connection between the copper pillars to die pad substrates. The most common defect, which is solder void formation at the solder joint area, will reduce the interconnection strength or robustness of the solder joint. To understand the solder void formation mechanism, a simulation experiment has been carried out by using copper and silver plated lead pad substrate for pillar solder joint formation process at different stress time interval. An analytical analysis by using 3D CT-scan has been carried out to detect the submicron size solder void defect, especially during high-temperature stress process. An elemental analysis by energy dispersive X-ray also has been carrying out to prove the substrate pad material dissolution mechanism during solder joint formation. With the experiment finding and deeply understanding the material dissolution behavior in packaging concept, this can ensure more robust pillar joint die bond process and guarantee quality packages built.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114822308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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