A 0.5-V 1.13-μW/channel neural recording interface with digital multiplexing scheme

Abstract

This paper presents a power-efficient system architecture for the design of multiple-channel neural recording interface. A new multiple-channel SAR ADC is proposed to facilitate multiplexing among channels, thus eliminates the need for analog multiplexer and associated buffers. The proposed ADC is verified through a 16-channel recording chip fabricated in a standard 0.13-μm CMOS technology with an active area of 1.17 mm2. The chip consumes 18 μW from a 0.5-V supply and attains a noise efficiency factor of 3.09. The average per channel power and area are 1.13 μW and 0.073 mm2, respectively, which are the lowest among existing multiple-channel designs.