On-chip protection for automotive integrated circuits robustness

Abstract

On-chip protection architecture for automotive ICs (integrated circuits) system-level robustness is introduced. It comprises three-level protection for interface pins with high bidirectional voltage swing. A first protection stage is optimized to sustain the largest portion of the ESD (electrostatic discharge) and EMI (electromagnetic interference)-induced stress. A second-level protection stage is customized to sustain the relatively lower IC-level ESD stress, and the third level protection stage absorbs the initial transient voltage impulse.