M. Dahl, J. Babb, Russell Tessier, S. Hanono, D. Hoki, Anant Agarwal
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引用次数: 18
Abstract
Describes a complete FPGA-based emulation software system using Virtual Wires technology and present the results of emulating an 18K-gate ASIC implementation of a modified Sparc microprocessor. Virtual Wires overcomes the pin-count limitation that formerly restricted the efficiency of FPGA-based logic emulators. The MIT Virtual Wires softwire compiler accepts a netlist description of the system to be emulated and produces programming information for the FPGA hardware, an inexpensive ($3000) board designed for Virtual Wires in-circuit emulation. The compiler also provides an interface to standard logic simulator tools for hardware accelerated simulation. We discuss innovative features of the compiler system and knowledge gained during its construction. A comparison is made of different implementations of the on-chip Virtual Wires circuitry synthesized by the compiler. Several enhancements to the original Virtual Wires concept are presented that improve the emulation speed and FPGA utilization.<>
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