Design Area-time Efficient Pipeline Architecture for Finite Impulse Recursive System

Abstract

The paper aims in developing a finite impulse response filter architecture that relies on the multipliers to overcome the shortcomings in the prevailing method and heighten the speed of the filters by employing the adders. The algorithm of the Vedic multiplier is generally utilized for the applications of higher bit length were the lower order bits work well with the ordinary multiplier. The Vedic multiplier and the ordinary multiplier is integrated to develop a multiplier of higher speed for an applications with the higher bit length. The bits of the remainders are eluded to reduce the issues faced in the prevailing architecture. The proffered algorithm is implemented using the Xilinx software Vertex-7.