Yongsheng Yin, Minglun Gao, Honghui Deng, Shangquan Liang, Cong Liu
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引用次数: 3
Abstract
A 14-bit, 130MSPS DAC with 2times FIR interpolation filter simulated in a 0.35 mum CMOS process is described in this paper. The DAC adopts segmented current-steering structure, which combines the characteristic of unit current DAC and the binary weighted DAC to get the balance between area and performance. A 2times FIR interpolation filter is introduced to reduce the complexity of analog reconstruction filter following the DAC. Key circuits and simulation results are presented. The results show that this DAC can deliver up to 20 mA current into a 50Omega load. Power dissipation with 3.3 V supply is 286 mW at 200 MHz DAC update rate. The INL is plusmn3.5LSB, and DNL is plusmn 2.0LSB. SFDR is 76 dB at 100 MSPS and 50 MHz output frequency.
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