Fabrication of poly-silicon microwire using conventional photolithography technique: Positive resist mask vs aluminium hard mask

M. Nuzaihan, U. Hashim, T. Nazwa, A. R. Ruslinda
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引用次数: 4

Abstract

We have demonstrated a simple and low-cost method to fabricate poly-silicon microwire by conventional photolithography technique. There are two different steps process flow were involved in the conventional photolithography technique which are employed the positive resist as a mask and aluminium (Al) as hard mask. Low pressure chemical vapour deposition (LPCVD) was used to deposit 50 nm poly-silicon layer on the Si-SiO2-Si3N4 layer. Wire mask must be first designed using AutoCAD before patterning onto chrome mask. Initially the 300 nm thick layer of positive resist is coated on the sample. Subsequently, the coated sample were exposed to UV light for 10 seconds and followed by development process. The critical part in this development process is to control the development time and resist profile. There are three types of resist profile problems such as underdevelopment, incomplete development and overdevelopment resist profile. These resist profiles problems can negatively affect in the subsequent etch process. Next process is an etching process. For positive resist as a mask process flow, the developed sample was loaded into SAMCO Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE) 10iP to anisotropic etching of poly-silicon for 7 seconds. Meanwhile, for Al as a hard mask, the developed sample was dipped into Aluminium (Al) etchant for 3 minutes then followed by resist stripping and anisotropic etching of poly-silicon as similar to the resist mask process flow. Finally, the dimensions and etch profiles of <; 1um poly-silicon microwire were morphologically characterized using optical microscopy.
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利用传统光刻技术制备多晶硅微丝:正阻掩膜与铝硬掩膜
我们展示了一种简单和低成本的方法,以传统的光刻技术制造多晶硅微线。传统的光刻技术有两种不同的工艺流程,即采用正极抗蚀剂作为掩膜和铝(Al)作为硬掩膜。采用低压化学气相沉积(LPCVD)技术在Si-SiO2-Si3N4层上沉积了50 nm的多晶硅层。钢丝遮罩必须先用AutoCAD设计,然后再在镀铬遮罩上进行图案设计。最初300nm厚的正极抗蚀剂层被涂在样品上。随后,将涂层样品暴露在紫外线下10秒,然后进行显影过程。该开发过程的关键部分是控制开发时间和抗配置文件。抗蚀性剖面问题主要有抗蚀性剖面发育不足、不发育和过发育三种类型。这些抗蚀剂轮廓问题会对随后的蚀刻工艺产生负面影响。下一道工序是蚀刻工序。将制备好的样品加载到SAMCO电感耦合等离子体反应离子刻蚀(ICP-RIE) 10iP中,进行多晶硅的各向异性刻蚀7秒。同时,对于Al作为硬掩膜,将显影样品浸入铝(Al)蚀刻剂中3分钟,然后进行抗蚀剂剥离和多晶硅的各向异性蚀刻,类似于抗蚀剂掩膜的工艺流程。最后,给出了<;利用光学显微镜对1um多晶硅微丝进行了形貌表征。
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