{"title":"Implementing grayscale morphological operators with a compact ranked order extractor circuit","authors":"J. Poikonen, A. Paasio","doi":"10.1109/CNNA.2002.1035107","DOIUrl":null,"url":null,"abstract":"Mathematical morphology provides tools for many image processing tasks. In this paper we discuss the implementation of grayscale morphological operators of erosion, dilation and reconstruction with a hardware efficient ranked order filter circuit. By using dedicated hardware for these basic operations a higher performance of processing more complex functions in a massively parallel processor array can be achieved. Because the circuit realization of the ranked order filter used is very compact, the area required for one processing cell can be kept low. Simulations of the operation were performed with a 0.18 /spl mu/m digital CMOS technology.","PeriodicalId":387716,"journal":{"name":"Proceedings of the 2002 7th IEEE International Workshop on Cellular Neural Networks and Their Applications","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2002-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2002 7th IEEE International Workshop on Cellular Neural Networks and Their Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CNNA.2002.1035107","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
Mathematical morphology provides tools for many image processing tasks. In this paper we discuss the implementation of grayscale morphological operators of erosion, dilation and reconstruction with a hardware efficient ranked order filter circuit. By using dedicated hardware for these basic operations a higher performance of processing more complex functions in a massively parallel processor array can be achieved. Because the circuit realization of the ranked order filter used is very compact, the area required for one processing cell can be kept low. Simulations of the operation were performed with a 0.18 /spl mu/m digital CMOS technology.