Implementing grayscale morphological operators with a compact ranked order extractor circuit

J. Poikonen, A. Paasio
{"title":"Implementing grayscale morphological operators with a compact ranked order extractor circuit","authors":"J. Poikonen, A. Paasio","doi":"10.1109/CNNA.2002.1035107","DOIUrl":null,"url":null,"abstract":"Mathematical morphology provides tools for many image processing tasks. In this paper we discuss the implementation of grayscale morphological operators of erosion, dilation and reconstruction with a hardware efficient ranked order filter circuit. By using dedicated hardware for these basic operations a higher performance of processing more complex functions in a massively parallel processor array can be achieved. Because the circuit realization of the ranked order filter used is very compact, the area required for one processing cell can be kept low. Simulations of the operation were performed with a 0.18 /spl mu/m digital CMOS technology.","PeriodicalId":387716,"journal":{"name":"Proceedings of the 2002 7th IEEE International Workshop on Cellular Neural Networks and Their Applications","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2002-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2002 7th IEEE International Workshop on Cellular Neural Networks and Their Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CNNA.2002.1035107","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6

Abstract

Mathematical morphology provides tools for many image processing tasks. In this paper we discuss the implementation of grayscale morphological operators of erosion, dilation and reconstruction with a hardware efficient ranked order filter circuit. By using dedicated hardware for these basic operations a higher performance of processing more complex functions in a massively parallel processor array can be achieved. Because the circuit realization of the ranked order filter used is very compact, the area required for one processing cell can be kept low. Simulations of the operation were performed with a 0.18 /spl mu/m digital CMOS technology.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
实现灰度形态算子与一个紧凑的排序顺序提取电路
数学形态学为许多图像处理任务提供了工具。本文讨论了用硬件高效的秩序滤波电路实现侵蚀、膨胀和重构的灰度形态算子。通过为这些基本操作使用专用硬件,可以实现在大规模并行处理器阵列中处理更复杂功能的更高性能。由于所采用的排序滤波器的电路实现非常紧凑,因此可以保持一个处理单元所需的面积很低。采用0.18 /spl mu/m的数字CMOS技术进行了仿真。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Non-saturated binary image learning and recognition using the ratio-memory cellular neural network (RMCNN) Analogic preprocessing and segmentation algorithms for off-line handwriting recognition Statistical error modeling of CNN-UM architectures: the binary case Realization of couplings in a polynomial type mixed-mode CNN Configurable multi-layer CNN-UM emulator on FPGA
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1