Transparent BIST for ECC-based memory repair

Abstract

Embedded memories occupy the largest part of modern SoCs and include an even larger amount of transistors. As memories are designed very tightly to the technology limits, they are more prone to failures than other circuits. Thus, they concentrate the large majority of fabrication defects affecting yield adversely. Defect densities are expected to sharply increase in ultimate CMOS and post CMOS processes, resulting in high defect densities. These problems will further worsen due to stringent low-power constraints requiring drastic reduction of voltage levels. To cope with the resulting high defect densities in cost effective manner, ECC-based repair combining ECC with spare words becomes mandatory. On the other hand, coping with accelerating aging may require testing the memories during application execution, making mandatory transparent BIST Nevertheless, traditional implementations of transparent BIST do not comply with the constraints of ECC-based repair. To cope with this issue the paper proposes a transparent BIST architecture compliant with ECC-based repair.