Effect of temperature and exposure to moisture on leakage through VDP liners in TSV structures

Abstract

Bake recoverable leakage in TSV (Through Silicon Via) structures was studied as a function of annealing and exposure to damp heat. It was demonstrated, unexpectedly, that moisture was not the source of the leakage as had been observed previously in integrated circuits. The data generated here suggests a new phenomenon not related to absorbed moisture. The test data, while not determining a cause, shows no correlation (in the VDP material tested) between an initial bump in leakage current and chemisorbed moisture. Despite that, a link between a bump in initial leakage current and an unknown vector (possibly an absorbed solvent other than water) was in fact found.