Assessment of SiGe/Si heterojunction tunnel field-effect transistor for digital VLSI circuit applications

Abstract

In this chapter, we report p+-n+-i-n+ (n -type) and n+-p+-i-p+ (p -type) SiGe/Si hetero double gate tunnel field-effect transistor (TFET) (H-DGTFET) for low power circuit applications. To achieve the optimum performance of the above devices, the Silicon (Si) and Germanium (Ge) composition of 30% and 70% (SiO3 Ge0.7), respectively, considered in source region, and a heavily doped (HD) layer placed in the channel near the source-channel junction are employed. Due to lower tunnel resistance offered by SiGe, the technology computer aided design (TCAD) device simulations of both the configurations show superior results in terms of DC and analog/radio frequency (RF) parameters as compared to the conventional TFETs. However, linearity of n-type device is analyzed in terms of VIP2, VIP3, and PldB. Furthermore, the circuit-level performance assessment is done by implementing complementary primary digital circuits (such as an inverter, NAND, and NOR logics) using lookup table-based Verilog-A model of the H-DGTFET. Comparison table shows impressive results in terms of digital performance parameters such as static noise margin (SNM), noise margin high (NMH ), noise margin low (NML ), high-to -low delay (τphl ), low-to-high delay (τphl,), and propagation delay (τp) as compared to the recently reported work