Zhang Haipeng, Geng Lu, Lin Mi, Zhan Zhonghai, Lu Weifeng, Wang Xiaoyuan, Wang Ying, Zhang Qiang, B. Jianling, Wang Dejun
{"title":"High Voltage InGaN/GaN/AlGaN RTD Suitable for ESD Protection Applications of GaN/InGaN-based Devices and ICs Validated by Simulation Results","authors":"Zhang Haipeng, Geng Lu, Lin Mi, Zhan Zhonghai, Lu Weifeng, Wang Xiaoyuan, Wang Ying, Zhang Qiang, B. Jianling, Wang Dejun","doi":"10.1109/IPFA.2018.8452592","DOIUrl":null,"url":null,"abstract":"A novel high voltage InGaN/GaN/AlGaN RTD was proposed for ESD protection of GaN/InGaN-based devices and ICs. The proposed RTD consists of a sandwiched $\\text{In}_{0.21}\\text{Ga}_{0.79}\\mathrm{N}/\\text{GaN}/\\text{In}_{0.14}\\text{Ga}_{0.86}\\mathrm{N}/\\mathrm{A}1_{0.1}\\text{Ga}_{0.9}\\mathrm{N}$ DBS structure on a GaN/InGaN substrate with N-original surface. Simulation experiments indicated that the proposed RTD samples are characterized of high forward block voltages at about 7.38 V, low leakage forward currents less than $10^{-38}\\mathrm{A}/\\mu \\mathrm{m}^{2}$ and $10^{-39}\\mathrm{A}/\\mu \\mathrm{m}^{2}$ and high reverse current densities up to the order of $10^{-5}\\mathrm{A}/\\mu \\mathrm{m}^{2}$ at about −2.55 V bias voltage and beyond $10^{-4}\\mathrm{A}/\\mu \\mathrm{m}^{2}$ at about −2.8 V bias voltage respectively. Analysis on HBM mode ESD circuits indicated that they can be simplified into ideal one order RC loop. This is because that the resistance of the proposed high voltage (HV) RTD pair at on-state is ignorable relative to discharging resistance R1 whether considering its parasitic capacitance or not. As a result, the sample 1 with junction area of $120\\times 120\\mu \\mathrm{m}^{2}$ is large enough to protect the chip from ESD damaging up to $\\pm 2000$ V ESV swash in ideal 840 ns. As for sample 2, its junction area of $380\\times 380\\mu \\mathrm{m}^{2}$ is capable of providing the same strength of ESD protection as that of sample 1. As the parasitic capacitance of sample 2 was considered through analyses of charge variations in emitter region, quantum well region and collector region with bias voltage, the results indicate that the big signal differential parasitic floating capacitance of quantum region is about -0.178/-0.174 pF/cm2, which is negligible comparing with stand ESV capacitance of HBM mode ESD protection applications. Its function is to shielding the influence of applied voltage on the potential of the quantum well. Its attenuation factor of voltage is not more than −23.6 dB.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2018.8452592","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A novel high voltage InGaN/GaN/AlGaN RTD was proposed for ESD protection of GaN/InGaN-based devices and ICs. The proposed RTD consists of a sandwiched $\text{In}_{0.21}\text{Ga}_{0.79}\mathrm{N}/\text{GaN}/\text{In}_{0.14}\text{Ga}_{0.86}\mathrm{N}/\mathrm{A}1_{0.1}\text{Ga}_{0.9}\mathrm{N}$ DBS structure on a GaN/InGaN substrate with N-original surface. Simulation experiments indicated that the proposed RTD samples are characterized of high forward block voltages at about 7.38 V, low leakage forward currents less than $10^{-38}\mathrm{A}/\mu \mathrm{m}^{2}$ and $10^{-39}\mathrm{A}/\mu \mathrm{m}^{2}$ and high reverse current densities up to the order of $10^{-5}\mathrm{A}/\mu \mathrm{m}^{2}$ at about −2.55 V bias voltage and beyond $10^{-4}\mathrm{A}/\mu \mathrm{m}^{2}$ at about −2.8 V bias voltage respectively. Analysis on HBM mode ESD circuits indicated that they can be simplified into ideal one order RC loop. This is because that the resistance of the proposed high voltage (HV) RTD pair at on-state is ignorable relative to discharging resistance R1 whether considering its parasitic capacitance or not. As a result, the sample 1 with junction area of $120\times 120\mu \mathrm{m}^{2}$ is large enough to protect the chip from ESD damaging up to $\pm 2000$ V ESV swash in ideal 840 ns. As for sample 2, its junction area of $380\times 380\mu \mathrm{m}^{2}$ is capable of providing the same strength of ESD protection as that of sample 1. As the parasitic capacitance of sample 2 was considered through analyses of charge variations in emitter region, quantum well region and collector region with bias voltage, the results indicate that the big signal differential parasitic floating capacitance of quantum region is about -0.178/-0.174 pF/cm2, which is negligible comparing with stand ESV capacitance of HBM mode ESD protection applications. Its function is to shielding the influence of applied voltage on the potential of the quantum well. Its attenuation factor of voltage is not more than −23.6 dB.