Sub-Threshold Design: The Challenges of Minimizing Circuit Energy

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI:10.1145/1165573.1165661

B. Calhoun, Alice Wang, N. Verma, A. Chandrakasan

引用次数: 63

Abstract

In this paper, we identify the key challenges that oppose sub-threshold circuit design and describe fabricated chips that verify techniques for overcoming the challenges

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亚阈值设计:最小化电路能量的挑战

在本文中，我们确定了反对亚阈值电路设计的关键挑战，并描述了验证克服这些挑战的技术的制造芯片

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design

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