The multi-associative branch target buffer: a cost effective BTB mechanism

Abstract

A new branch target buffer hardware organization, denoted as the multi-associative branch target buffer (MBTB), for efficient branch handling in pipelined central processing units (CPUs) is presented. The proposed organization consists of multiple different size arrays addressed via a bit selection addressing mechanism. These arrays are used to maintain information pertinent to the branches, including information usually contained within the traditional branch target buffers such as branch instruction address and branch target address. The proposed configuration and its bit extraction mechanism — which is used to increase the hit ratio of the buffers — provides the capability of dynamically increasing the associativity of the branch target buffers. Due to the new organization, i.e. the multiple array structure, along with the new addressing scheme, it is suggested, based on simulation results, that improvements with reduced hardware can be expected when a multi-associative branch target buffer is installed in a CPU implementation.