Digital array receiving channel performance measurement system

Jihong Yan, Yuqing Ma, Zishu He
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Abstract

Digital array radar (DAR) is an important tendency of phased array radar (PAR). Since the DAR is equipped with many transmitting and receiving channels, the effectiveness of digital beam-forming (DBF) is affected by the channel performance. Thus, it is important to test the channel performance and calibrate the possible channel mismatch of each digital T/R modules before assembling. In this paper, a CPCI interface based on the channel performance measurement is introduced. In the hardware design of the system, FPGA is employed as a core for data accusation and storage through optical interface. The CPCI chip is used as the interface between the data acquisition board and PC. Under the control of computer application programs, the collected data are transferred back to the computer, in which the waveform analysis in both time and frequency domain and the calculation of the channel performance metrics are performed. The test results show the effectiveness and feasibility of the proposed design method.
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数字阵列接收信道性能测量系统
数字阵列雷达(DAR)是相控阵雷达(PAR)的一个重要发展方向。由于雷达具有多个发射和接收信道,信道性能直接影响数字波束形成的效果。因此,在组装之前测试通道性能并校准每个数字T/R模块可能的通道不匹配是很重要的。本文介绍了一种基于信道性能测量的CPCI接口。在系统的硬件设计中,采用FPGA作为核心,通过光接口进行数据采集和存储。CPCI芯片作为数据采集板与PC机之间的接口。在计算机应用程序的控制下,将采集到的数据传回计算机,进行时域和频域的波形分析和信道性能指标的计算。试验结果表明了所提设计方法的有效性和可行性。
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