A comparative analysis of optimized low-power comparators for biomedical-ADCs

Abstract

Comparators are essential blocks in implementing analog-to-digital converters (ADCs). An energy-efficient ADC such as successive approximation register (SAR) ADC or dual-slope ADC requires at least one comparator, where the power consumption mainly depends on the comparator design. This paper investigates various implementation techniques of low-power comparators emphasizing on their design performance metrics, and trade-offs such as sampling frequency, resolution, and power consumption. The proposed comparative analysis covers a recently published low power comparators for bio-signals monitoring and proposes a basic optimization method for these comparators. These comparators are redesigned using UMC 130nm CMOS technology for a fair comparison to present a good reference for proper choosing of a low power comparator that serves low-power bio-medical applications.