Slack analysis in the system design loop

Girish Venkataramani, S. Goldstein
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Abstract

We present a system-level technique to analyze the impact of design optimizations on system-level timing dependencies. This technique enables us to speed up the design cycle by substituting, in the design the loop, the time-consuming simulation step with a fast timing update routine. As a result, we can significantly reduce the design time from on the order of hours/days to the order of seconds/minutes. The update algorithm is defined on the Transaction Level Model (TLM) and can be used by any design flow that invokes TLM-based optimizations. This algorithm has linear-time complexity in the program size and experimental results indicate that any loss of accuracy due to this technique is negligible (< ±1%); the benefit is a reduction in total design cycle time from several hours to a matter of seconds.
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系统设计回路中的松弛分析
我们提出了一种系统级技术来分析设计优化对系统级时间依赖性的影响。这种技术使我们能够通过用快速定时更新例程代替设计循环中耗时的仿真步骤来加快设计周期。因此,我们可以将设计时间从数小时/天减少到数秒/分钟。更新算法是在事务级别模型(Transaction Level Model, TLM)上定义的,任何调用基于TLM的优化的设计流都可以使用它。该算法在程序大小上具有线性时间复杂度,实验结果表明,由于该技术导致的任何精度损失都可以忽略不计(<±1%);这样做的好处是将总设计周期从几个小时缩短到几秒钟。
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