Chip EOS issue analysis in board-level application

Abstract

Based on the analysis of field customer failure feedback data over years, it is found almost 50% of the chip failure in board-level is EOS (electrical over stress) issue. Hence it is very common chip failure mode. From board-level point of view, EOS can destroy a semiconductor chip in many ways, resulting in observable and different failure attributes. Thus it is really challenging to identify and find the root cause when it happens at board-level. Also, EOS burns up the chip, and can be caused by several additional factors at board level. It makes EOS event become more complex for investigation and analysis. In this paper, from several case studies, we can classify EOS issues are due to “chip undetectable weakness”, “board-level application” or “board environment” and summarized few conclusions for chip EOS issue.