{"title":"A 10-bit 100-MS/s 2b/cycle-assisted SAR ADC in 180nm CMOS","authors":"Yung-Hui Chung, Hua-Wei Tseng","doi":"10.1109/EDSSC.2017.8126418","DOIUrl":null,"url":null,"abstract":"This paper presents a 10-bit 100-MS/s 2b/cycle-assisted SAR ADC in a 180nm CMOS technology. The proposed 2b/cycle-assisted architecture can effectively speed up ADC operation and improve the ADC linearity. To maintain a small capacitor mismatch, dual-reference C-DACs are proposed to avoid using a tiny unit capacitance. At 100-MS/s, it consumes 6.45 mW from a 1.8-V supply. Measured Nyquist SNDR and SFDR are 52.3 and 71 dB, respectively. Measured ENOB is 8.4 bits, equivalent to a FoM of 191 fJ/conversion-step.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2017.8126418","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
This paper presents a 10-bit 100-MS/s 2b/cycle-assisted SAR ADC in a 180nm CMOS technology. The proposed 2b/cycle-assisted architecture can effectively speed up ADC operation and improve the ADC linearity. To maintain a small capacitor mismatch, dual-reference C-DACs are proposed to avoid using a tiny unit capacitance. At 100-MS/s, it consumes 6.45 mW from a 1.8-V supply. Measured Nyquist SNDR and SFDR are 52.3 and 71 dB, respectively. Measured ENOB is 8.4 bits, equivalent to a FoM of 191 fJ/conversion-step.
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