A low power analog channel decoder for Ultra Portable Devices in 65 nm technology

Abstract

This paper presents the architecture and the corresponding simulation results for a digitally interfaced ultra-low power extended Hamming decoder implemented in analog integrated circuitry. ST's 65nm low power CMOS design library was used to simulate the complete decoder including a serial input digital interface, an analog decoding core and a serial output digital interface. The simulated bit error rate (BER) performance of the decoder is presented and compared to the ideal performance of the Hamming code. Transistor-level simulation results show that an ultra low power, high throughput Hamming decoder up to 2.5 Mb/s can be implemented using analog circuitry working in sub-threshold (sub-VT ) region with a total power consumption below 40 µW. The decoder consumes less than 16 µW when a lower throughput of 250 kb/s is desired.